I'm using Coregen on XC2S200 to generate a 6144
bytes (12 blocks)
BRAM and I get these infos:

INFO:Xst:2260 - The FF/Latch <BU16> in Unit <test> is
equivalent to the following 3 FFs/Latches : <BU97> <BU178> <BU259>

INFO:Xst:2260 - The FF/Latch <BU19> in Unit <test> is
equivalent to the following 3 FFs/Latches : <BU100> <BU181> <BU262>

INFO:Xst:2260 - The FF/Latch <BU16> in Unit <test> is
equivalent to the following 3 FFs/Latches : <BU97> <BU178> <BU259>

INFO:Xst:2260 - The FF/Latch <BU19> in Unit <test> is
equivalent to the following 3 FFs/Latches : <BU100> <BU181> <BU262>


I didn't create those BUxx FF/Latches, presumably they are internal to ISE.

6144 bytes requires 13 address lines and 2^13 = 8192 which means that
I can actually access the same memory with diff. addresses.
Is that what ISE is trying to tell me? Because, if I create,
for example, 1025 (1024+1) bytes BRAM w/ 11 address lines
then I don't get those infos.

Using ISE 10.1.03 

On Jul 6, 3:09=A0pm, "aleksa"
<aleks...@gmail.com> wrote:
> I'm using Coregen on XC2S200 to generate a 6144 bytes (12 blocks)
> BRAM and I get these infos:
>
> INFO:Xst:2260 - The FF/Latch <BU16> in Unit <test> is
> equivalent to the following 3 FFs/Latches : <BU97> <BU178> <BU259>
>
> INFO:Xst:2260 - The FF/Latch <BU19> in Unit <test> is
> equivalent to the following 3 FFs/Latches : <BU100> <BU181>
<BU262>
>
> INFO:Xst:2260 - The FF/Latch <BU16> in Unit <test> is
> equivalent to the following 3 FFs/Latches : <BU97> <BU178> <BU259>
>
> INFO:Xst:2260 - The FF/Latch <BU19> in Unit <test> is
> equivalent to the following 3 FFs/Latches : <BU100> <BU181>
<BU262>
>
> I didn't create those BUxx FF/Latches, presumably they are internal to IS=
E.
>
> 6144 bytes requires 13 address lines and 2^13 =3D 8192 which means that
> I can actually access the same memory with diff. addresses.
> Is that what ISE is trying to tell me? Because, if I create,
> for example, 1025 (1024+1) bytes BRAM w/ 11 address lines
> then I don't get those infos.
>
> Using ISE 10.1.03

Never try to second-guess the inner workings of Coregen.  These cores
are not optimised
and generally give more warnings due to unconnected ports, etc.  Learn
to live with
the warnings as long as the memory does what you want.  If I had to
guess, the "info's"
happen when you have enough memory defined to require fabric-based
multiplexing
rather than just a bunch of instantiated block RAM primitives.

The "BU..." are very informative names generated in loops in the
coregen code ;-)
I generally ignore all warnings with BU in the net names.  If you
don't want to
have warnings, generate your own RAM's using inference or instantiated
primitives.

Regards,
Gabor