Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST


Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | How to declare a port with a new type

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

How to declare a port with a new type - Weng Tianxiang - 2010-07-07 11:07:00

Hi,
I am in VHDL.

I have the following statements:

type integer_array is array(natural range <>) of integer;
type cs_type is array (0 to N) of integer_array (1 to Nmax);
signal cs : cs_type;

If those statements live within an architecture, everything goes well.

But if I make the signal cs as a port of the entity, the problem
arise:

I must specify integer_array and  cs_type somewhere in the project
globally.

Is anything I can do to use the type declarations locally in the file
of the entity?

Thank you.

Weng





Re: How to declare a port with a new type - Martin Thompson - 2010-07-07 12:08:00

Weng Tianxiang <w...@gmail.com> writes:

> Hi,
> I am in VHDL.
>
> I have the following statements:
>
> type integer_array is array(natural range <>) of integer;
> type cs_type is array (0 to N) of integer_array (1 to Nmax);
> signal cs : cs_type;
>
> If those statements live within an architecture, everything goes well.
>
> But if I make the signal cs as a port of the entity, the problem
> arise:
>
> I must specify integer_array and  cs_type somewhere in the project
> globally.
>
> Is anything I can do to use the type declarations locally in the file
> of the entity?

You have to put them in a package.  The package can exist within the
same file as the entity though.  Then things which instantiate that
entity can make use of the package to see the same definitions.

Be aware - just because it's in the same file doesn't mean you don't
have to do:

   use work.my_package.all; 

before the entity declaration!

Also be aware that if you put the package in the same file and compile
the file "normally", you'll have to recompile anything which depends
on the that package (as it's been touched). If you're using Modelsim,
you can use 

   vcom -just bac myfile.vhd

to compile just the package bodies, architetcures and configs, which
doesn't touch the package and entity declarations, which then don't
ripple on to other files.

If your compiler can't do something similar, you may be better to put
the package (and probably the entity) in a separate file to the
architecture, as it's the architecture which get's the most iteration
during the development of the code, and it's great to only have to
recompile the one file most of the time.

Cheers,
Martin

-- 
m...@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware