Hello!
I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chainon a custom board. The problem is when i program my FPGAs through JTAGinterface, FPGA 1 always gets programmed and verified and always showsoutput whereas FPGA 2 always gets programmed and verified and sometimes itshows the output and sometimes it doesnt.

I have failed to understand the reason for this behavior :s

Kindly help me .. thanks	   
					
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On Jul 15, 3:11=A0am, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Hello!
> I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain
> on a custom board. The problem is when i program my FPGAs through JTAG
> interface, FPGA 1 always gets programmed and verified and always shows
> output whereas FPGA 2 always gets programmed and verified and sometimes i=
t
> shows the output and sometimes it doesnt.
>
> I have failed to understand the reason for this behavior :s
>
> Kindly help me .. thanks =A0 =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Do you always program them in sequence after power-up?

If you randomly reprogram the devices well after the initial program,
you could be getting trouble from an open-drain configuration I/O pin
connected in common between the two chips.  To program chips in a
chain independently after power up in the Xilinx chain I used a couple
years back, assertion of the program pin causes the done pin to go low
which confuses the other chip as an input.

Yes i always program it in a sequence i.e. FPGA 1
and then FPGA 2. 
another point i missed in the last post is that while programming FPGA 1, igive it the bit file with DRIVE DONE = YES, and when i program FPGA 2 , igive it the bit file with DRIVE DONE = YES.

When i give FPGA 1 the bit file with DRIVE DONE = NO, it doesn't getprogrammed and FPGA 2 shows the same random behavior as mentioned above.and when i reprogram FPGA 1 after FPGA 2 , FPGA 1 gets programmed. Now,there's something fishy going around with the DONE signal i guess, but i'mnot sure about it so i need pointers, help, anything that would give alead. 

Thanks John =)	   
					
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On Jul 16, 5:18=A0am, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
<snip>
>
> there's something fishy going around with the DONE signal i guess, but i'=
m
> not sure about it so i need pointers, help, anything that would give a
> lead.
>
> Thanks John =3D) =A0 =A0

Read up on the DONE signal and its effect as an *input* to the FPGA.

Note that it gets pulled down (regardless of drive=3Dyes or no, I
believe) when the program bit is first asserted.  One way to avoid
this interaction is to break out the done separately from the two
FPGAs so the open-drain pull-down of the DONE signal on one device
doesn't affect the operation of the second; rather than one DONE
connection to your programming device (assuming you're not programming
via cable) you use two.

Also look at whether DRIVE DONE =3D YES actively tries to assert the
DONE pin even if the DONE from the other chip drives the same line
with a typically-stronger pull down.  Typical use is to have the DONE
pulled up with a resistor and leave the rising edge for when all
devices are programmed.  The DRIVE DONE =3D YES would be for non-ganged
DONE pins such as a single FPGA or separately pinned out DONE signals
for the individual FPGAs so you don't have to add the pull-up to the
single driver.

Another thing, when the FPGA 2 gets programmed
and i read its statusregister, it looks perfectly in accordance to a working FPGA's status wordbut it doesn't show any output. Is it possible that FPGA 2 never comes outof the startup sequunce ?
	   
					
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On 16 July, 11:42, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Another thing, when the FPGA 2 gets programmed and i read its status
> register, it looks perfectly in accordance to a working FPGA's status wor=
d
> but it doesn't show any output. Is it possible that FPGA 2 never comes ou=
t
> of the startup sequunce ?
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

On the face of it your having the same results as I had and it was all
straightforward. An unprogrammed FPGA drives done low using open
drain. When you program them they fail at the very last point " I am
now programmed, I have released done but done is still low so I will
not start working". All I did was programmed each FPGA using JTAG but
only when you program the last FPGA does done go high and the FPGA
starts. Done is now not being driven low by anything and programming
any FPGA will make it work.

Typing "done pin" at xilinx.com and selecting the first hit explains
this fairly well.

Colin