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Comp.Arch.FPGA | 1-wire question

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

1-wire question - Giuseppe Marullo - 2010-07-15 09:10:00

HI all,
I would like to write a decoder for 1-wire but I am stuck about the 
search algorithm.

My question is: is it possible for a third party, without knowing the 
1-Wire master and "slave" status, to correctly decode the whole 
execution of the command?

I mean, the sequence of bits exhanged on the bus could give a clue of 
when is going to end or the exact informations are inside the master and 
you should wait the next reset because you cannot tell when it is going 
to end.

It is not clear what happens if the master has already a list of 
devices, would it be possible to understand what is going on?

BTW, which is the relation between 1-Wire commands and reset sequence?
Is it true that every command must start with a reset or it could be 
used also to end a command ?

Thanks in advance,

Giuseppe Marullo

g...@iname.com



Re: 1-wire question - jacko - 2010-07-16 01:49:00

On Jul 15, 2:10=A0pm, Giuseppe Marullo
<giuseppe.marullonos...@iname.com> wrote:
> HI all,
> I would like to write a decoder for 1-wire but I am stuck about the
> search algorithm.
>
> My question is: is it possible for a third party, without knowing the
> 1-Wire master and "slave" status, to correctly decode the whole
> execution of the command?
>
> I mean, the sequence of bits exhanged on the bus could give a clue of
> when is going to end or the exact informations are inside the master and
> you should wait the next reset because you cannot tell when it is going
> to end.
>
> It is not clear what happens if the master has already a list of
> devices, would it be possible to understand what is going on?
>
> BTW, which is the relation between 1-Wire commands and reset sequence?
> Is it true that every command must start with a reset or it could be
> used also to end a command ?
>
> Thanks in advance,
>
> Giuseppe Marullo
>
> giuseppe.maru...@iname.com

if reset go tristate for all but master.
on(clock) step through following
if not tristate emit address and command
process recieved command gated by address
if command invalid go to reset
if command required tristate switch then switch sender off
if command required tristate switch then switch reciever on
loop to on(clock)