Hello everyone,
I have a (maybe) simple problem I don't know exactly how to face up.

I am given a design (which is made by a third person) that realizes simplebus peripherals upon a Altera CPLD.
The design is quite simple: the address bus along with the data bus and theREAD signals are brought as inputs of the CPLD (outputs are notconsidered).
There is a combinatorial network which, starting from the adresses bus andthe READ signal, derives some internal Chip Select signals used to drivethe Clock of internal FFD registries.

Now, I am asked to perform timing analysis to such design to verify if itis feasible (I have the timing specs of the bus).
How can I perform such kind of *asynchronous* analysis? I am used toanalyze pure synchronous circuits, but this situation is totallydifferent!
Theoretically, I should verify that the propagation delay of thecombinatorial decoding network is compatible with the timings of the FFDs,but actually I do not know exactly the timings of the FFD (I suppose theyare not a fixed value but depend on the decisions of the place and route)

Paradoxically, I would be able to verify timings if the FFDs were realizedas physical chips OFF the CPLD (verifying that the pin-to-pin combinatorialdelay is feasible according to the external FFD chips timings).

How should I model such constrains when everything is modeled inside a CPLDdesign? I am currently using Quartus II tools.

Thank you in advance,
Primiano Tucci

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 Primiano Tucci
 http://www.primianotucci.com


	   
					
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