Hello All,

I have a requirement to build a SOC design with two Arm cores along
with some standard and custom peripherals.  The Actel Cortex-M1
enabled FPGA's appear to be ideal for my application because the
licensing fee is included in the price of the processor.

I have started playing around with the Libero tools to see how
processor development is done with them.  The Libero environment comes
with a tool called SmartDesign for assembling a processor system.  It
seems to work reasonably well for creating an initial system.  You
connect the pieces with a graphical editor and the tool outputs VHDL
(or Verilog) for synthesis and simulation.

Though fine for initial prototyping I do not like to use graphical
tools to maintain a delivered design.  It is just too likely that some
glitch will block me from doing what I want.  I prefer to enter and
maintain the design at the HDL level with just a text editor and
synthesis tool.

I looked at the VHDL that comes out of SmartDesign and it is typical
machine generated code.  Just a bunch of block instantiations
connected by meaningless signal names.  Here comes my question.

Using Actel tools can you work with the Arm/Amba processor IP directly
in HDL?  Is there a library of cores with documentation?  Any comments
are greatly appreciated.

Best wishes,

  Pete

On Jul 17, 8:17=A0pm, self
<pete.dud...@comcast.net> wrote:
> Hello All,
>
> I have a requirement to build a SOC design with two Arm cores along
> with some standard and custom peripherals. =A0The Actel Cortex-M1
> enabled FPGA's appear to be ideal for my application because the
> licensing fee is included in the price of the processor.
>
> I have started playing around with the Libero tools to see how
> processor development is done with them. =A0The Libero environment comes
> with a tool called SmartDesign for assembling a processor system. =A0It
> seems to work reasonably well for creating an initial system. =A0You
> connect the pieces with a graphical editor and the tool outputs VHDL
> (or Verilog) for synthesis and simulation.
>
> Though fine for initial prototyping I do not like to use graphical
> tools to maintain a delivered design. =A0It is just too likely that some
> glitch will block me from doing what I want. =A0I prefer to enter and
> maintain the design at the HDL level with just a text editor and
> synthesis tool.
>
> I looked at the VHDL that comes out of SmartDesign and it is typical
> machine generated code. =A0Just a bunch of block instantiations
> connected by meaningless signal names. =A0Here comes my question.
>
> Using Actel tools can you work with the Arm/Amba processor IP directly
> in HDL? =A0Is there a library of cores with documentation? =A0Any comment=
s
> are greatly appreciated.
>
> Best wishes,
>
> =A0 Pete

NO NO NO
the Actel cortex is preoptimized hard-macro block that can not be used
with other tools or modified directly.

you can of course use original arm cortex code if you have it (and
license)

Antti

I've been looking at this some more. I don't see
any technical hurdles
to maintaining my Actel Cortex-M1 design in strait VHDL.

The code that comes out of SmartDesign is standard structural VHDL
that I can edit and modify with just a text editor.  The only
inconvenience is the text formatting.  I think I will use a VHDL
beautifier like the one that exists in emacs to clean up all the
source.  Then I will further clean up the resulting code as needed
where I will be working.  As I see it, there is no need to clean up
parts of the source code that I am not modifying.

Really the machine generated code that comes out of SmartDesign is
pretty good. There are bad indentation and line breaks that can be
cleaned up with a beautifier. Beyond that the only ugly thing is the
port map assignments for busses.  The port maps break out every single
member of a bus and assign them individually. That really boosts the
size of source code and hurts readability.

I understand that the Cortex processor IP is a black box. I cannot get
access to the Cortex processor internal source code and retarget it
(without paying a lot of money).  I just want to maintain the system
VHDL using only a text editor. That looks to be entirely practical.