Sign in

Search Comp.Arch.FPGA

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Advertisement

Ads

See Also

DSP

Embedded Systems

Electronics

Comp.Arch.FPGA | Xilinx Plan Ahead question

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

Xilinx Plan Ahead question - pes - 2010-07-22 05:00:00

Hi,


I' m new to Plan Ahead 12.1 and I' ve some values of I/O Ports in red color.
It concerns DDR3 pins and values in red are Drive Strength (12*) and 
Slew Type (SLOW*).
What could be the signification?

Thanks

______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Xilinx Plan Ahead question - maxascent - 2010-07-22 11:45:00

DDR memory uses SSTL I/O and doesnt allow you to
specify the drivestrength. It seems to me that the I/O is setup wrong.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com