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Comp.Arch.FPGA | sdram stable clock
There are 4 messages in this thread.
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sdram stable clock - chinnathurai - 2010-07-26 07:53:00
1.What is a stable clock? 2.How can i generate using DCM in xilinx? or vhdl? --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: sdram stable clock - Uwe Bonnes - 2010-07-26 08:30:00
chinnathurai <chinnathurai.c@n_o_s_p_a_m.rediffmail.com> wrote: > 1.What is a stable clock? > 2.How can i generate using DCM in xilinx? or vhdl? What did you do to try to understand these problems? -- Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------______________________________
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Re: sdram stable clock - Andy Peters - 2010-07-26 16:48:00
On Jul 26, 4:53=A0am, "chinnathurai" <chinnathurai.c@n_o_s_p_a_m.rediffmail.com> wrote: > 1.What is a stable clock? It's what horses use to tell time. -a______________________________
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Re: sdram stable clock - KJ - 2010-07-26 17:27:00
On Jul 26, 4:48=A0pm, Andy Peters <goo...@latke.net> wrote: > On Jul 26, 4:53=A0am, "chinnathurai" > > <chinnathurai.c@n_o_s_p_a_m.rediffmail.com> wrote: > > 1.What is a stable clock? > > It's what horses use to tell time. > Thanks for today's best laugh KJ