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Comp.Arch.FPGA | problem in loading from flash to spartan-3 xc3s200

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

problem in loading from flash to spartan-3 xc3s200 - andfn - 2010-07-28 11:52:00

Hello, I'm learning to use FPGA, and i've
designed and realized someschematic
using spartan-3 xc3s200 (208 pin) and xcf01s, the last following UG332.pdfpag 68.

I'm using the xilinx ise 9.2 updated sp4, and a digilent programmer
like xilinx programmer.

In impact, the .bit and the mcs file was correctly created, and I canprogram
both devices without problems or error messages.

In particular, I can create the .mcs file for the flash, I can program
that, but when I turn off the power the FPGA can't load from the
flash.

I can program directly the flash and the program work well obviously until
I turn off the power.

I tried to see the signal CCLK (pin 104) with a scope but the signal wasalways high (I dont't see the 6Mhz clock..)

I've set the CCLK option in fpga startup option, and (6 default) asconfiguration rate.

I tryed to put to ground the pin 7 of XCF01S (cf connected to pin 207 ofthe xc3s200) but never happened.

I've realized two schematic and both have the same problem.

on the last schematic I've pulled high (2.5V) with a 4.7k resistor theprog_b, init_b pins, and to 3.3V with a 330 ohm the done pin.

the other schematic links are:

(flash)vcco = vccj = vccint = 3.3V

(fpga)M0,M1,M2,HSWAP_EN = ground

(flash)reset <-->(fpga)init_b
(flash)CF <--->(fpga)prog_b
(flash(D0)<--->(fpga)din
(flash(tdi)<--->(fpga)tdo
(flash)clk <--->(fpga)cclk

(flash)tdo <--->(programmer)tdo

(programmer)tms <--->(flash)tms
(flash)tms <--->82ohm <--->tms

(programmer)tck <--->(flash)tck
(flash)tck) <---> 82ohm <---> (fpga)tck

(programmer)tdi <---> 82ohm <---> (fpga)tdi

(programmer)vref <---> 3.3V

please, could you help me? thank you very much and regards.

andrea francovich


  

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com



Re: problem in loading from flash to spartan-3 xc3s200 - Gabor - 2010-07-28 13:44:00

On Jul 28, 11:52=A0am, "andfn"
<andfn@n_o_s_p_a_m.libero.it> wrote:
> Hello, I'm learning to use FPGA, and i've designed and realized some
> schematic
> using spartan-3 xc3s200 (208 pin) and xcf01s, the last following UG332.pd=
f
> pag 68.
>
> I'm using the xilinx ise 9.2 updated sp4, and a digilent programmer
> like xilinx programmer.
>
> In impact, the .bit and the mcs file was correctly created, and I can
> program
> both devices without problems or error messages.
>
> In particular, I can create the .mcs file for the flash, I can program
> that, but when I turn off the power the FPGA can't load from the
> flash.
>
> I can program directly the flash and the program work well obviously unti=
l
> I turn off the power.
>
> I tried to see the signal CCLK (pin 104) with a scope but the signal was
> always high (I dont't see the 6Mhz clock..)
>
> I've set the CCLK option in fpga startup option, and (6 default) as
> configuration rate.
>
> I tryed to put to ground the pin 7 of XCF01S (cf connected to pin 207 of
> the xc3s200) but never happened.
>
> I've realized two schematic and both have the same problem.
>
> on the last schematic I've pulled high (2.5V) with a 4.7k resistor the
> prog_b, init_b pins, and to 3.3V with a 330 ohm the done pin.
>
> the other schematic links are:
>
> (flash)vcco =3D vccj =3D vccint =3D 3.3V
>
> (fpga)M0,M1,M2,HSWAP_EN =3D ground
>
> (flash)reset <-->(fpga)init_b
> (flash)CF <--->(fpga)prog_b
> (flash(D0)<--->(fpga)din
> (flash(tdi)<--->(fpga)tdo
> (flash)clk <--->(fpga)cclk
>
> (flash)tdo <--->(programmer)tdo
>
> (programmer)tms <--->(flash)tms
> (flash)tms <--->82ohm <--->tms
>
> (programmer)tck <--->(flash)tck
> (flash)tck) <---> 82ohm <---> (fpga)tck
>
> (programmer)tdi <---> 82ohm <---> (fpga)tdi
>
> (programmer)vref <---> 3.3V
>
> please, could you help me? thank you very much and regards.
>
> andrea francovich
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

You don't really need much to be running to get a CCLK from the FPGA.
Check
that your mode pins (M0 M1 M2) are really low - if you use a resistor
to ground
these it should be less than 1K Ohms.  Other than that you need all
power
supplies (being able to program via JTAG seems to confirm these), and
proper
handling (pullups) on the PROG_B and INIT_B pins.  There are some
cases
where the power-on sequence of supplies can affect configuration.
These
are covered in ug332.  In any case pulling the PROG_B pin low
momentarily
should start the configuration even if there are power sequencing
issues.
So my top bet would be the mode pins.

HTH,
Gabor