I am working on a project where I need to
implement 6-th order Butterworth low-pass
filters in an FPGA. In some the bandwidth is
low relative to the input data rate, whereas
others have higher bandwidth. I can use ScopeIIR
or Matlab to give me a good idea of coefficient
accuracy for any given ratio of bandwidth to
input sample rate.

However, I'm not sure what data-path accuracy
I need (for 20-bit input / output accuracy).
Is there a rule-of-thumb I can use, or do I just
have to simulate the filter with real data and
see what gives me low enough noise?

I was planning on using biquads, but I'm not sure
whether I'm better off with DF1 or DF2 sections.

Thoughts?

Thanks

Pete

Pete Fraser wrote:

> I am working on a project where I need to
> implement 6-th order Butterworth low-pass
> filters in an FPGA. In some the bandwidth is
> low relative to the input data rate, whereas
> others have higher bandwidth. I can use ScopeIIR
> or Matlab to give me a good idea of coefficient
> accuracy for any given ratio of bandwidth to
> input sample rate.
> 
> However, I'm not sure what data-path accuracy
> I need (for 20-bit input / output accuracy).
> Is there a rule-of-thumb I can use, or do I just
> have to simulate the filter with real data and
> see what gives me low enough noise?
> 
> I was planning on using biquads, but I'm not sure
> whether I'm better off with DF1 or DF2 sections.

If the filter cutoff frequency is much lower then samplerate, then loss 
of precision in the direct implementation of the biquad section could be 
very roughly estimated as ~ Q (Fc/Fs)^2.

Let's say Fc = 100 kHz, Fs = 100 Hz, Q = 1. Loss of precision ~ 1e6 ~ 20 
bits. That is, if your filter is implemented with 32 bit data path, the 
result will be accurate only to 12 bits.

There are, of course, methods to get more accurate estimates and to 
improve precision, however this is a different and rather long story.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Pete Fraser <p...@covad.net> wrote:

>I am working on a project where I need to
>implement 6-th order Butterworth low-pass
>filters in an FPGA. In some the bandwidth is
>low relative to the input data rate, whereas
>others have higher bandwidth. I can use ScopeIIR
>or Matlab to give me a good idea of coefficient
>accuracy for any given ratio of bandwidth to
>input sample rate.
>
>However, I'm not sure what data-path accuracy
>I need (for 20-bit input / output accuracy).
>Is there a rule-of-thumb I can use, or do I just
>have to simulate the filter with real data and
>see what gives me low enough noise?

You should simulate the fixed-point filter.  When simulating,
you do not necessarily have to stimulate it with realistic data.  I 
often will stimulate the design being tested with bandlimited noise, and 
measure the RMS error of output (relative to the same design, but in full 
floating-point).  Plotting the RMS error (in dBc) vs. RMS input level
gives you a very good idea of the dynamic range of the fixed point
design.

>I was planning on using biquads, but I'm not sure
>whether I'm better off with DF1 or DF2 sections.

You can do this, or you can use a lattice topology
(called "ARMA" in matlab/fdatool), which is the most
well-behaved topology.

Steve

On Jul 29, 3:23=A0pm, "Pete Fraser"
<pfra...@covad.net> wrote:
> I am working on a project where I need to
> implement 6-th order Butterworth low-pass
> filters in an FPGA. In some the bandwidth is
> low relative to the input data rate, whereas
> others have higher bandwidth. I can use ScopeIIR
> or Matlab to give me a good idea of coefficient
> accuracy for any given ratio of bandwidth to
> input sample rate.
>
> However, I'm not sure what data-path accuracy
> I need (for 20-bit input / output accuracy).
> Is there a rule-of-thumb I can use, or do I just
> have to simulate the filter with real data and
> see what gives me low enough noise?
>
> I was planning on using biquads, but I'm not sure
> whether I'm better off with DF1 or DF2 sections.
>
> Thoughts?

i think you'll do better with DF1 sections (it will cost you two more
storage states, you'll have 8 instead of 6) and, for each section, an
accumulator that is wide enough to have no error given the word widths
of the signal (you said 20 bits) and the coefficients (that might
depend on the range of coefficients).

using 1st-order error shaping, a.k.a. "fraction saving" might gain you
something, and you can accomplish this for free if you leave in your
accumulator (as an initial value) the long-word output from the
previous sample.  you will need to compensate this by subtracting 1
from "a1", the first feedback coefficient.  then, for rounding to the
next section, all you need to do is truncate the low-order bits of the
word going to the next section, no rounding necessary (that gets fixed
with the fraction saving).  that means, for

  H(z) =3D N(z)/D(z)

where

 D(z) =3D  1 + a1*z^(-1) + a2*z^(-2)

      =3D  1 + (a1+1)*z^(-1) - z^(-1) + a2*z^(-2)

the term z^(-1) would be the double wide output from the previous
sample, y[n-1].


if your biquads remain resonant (meaning complex conjugate poles) and
if the resonant frequency is going to be very low and if the resonance
will be high (that is the poles are close to z=3D1), then consider
reworking the denominator of the biquad transfer function as:


 D(z) =3D  1 + a1*z^(-1) + a2*z^(-2)

      =3D  1 + (a1+2)*z^(-1) - 2*z^(-1) + (a2-1)*z^(-2) + z^(-2)


for the terms 2*z^(-1) and z^(-2), you would use the double-wide
previous states of y[n-1] and y[n-2].

just a recommendation i might make to make your life easier in the
universe of fixed-point arithmetic.

> Thanks

FWIW.

r b-j

On Jul 29, 8:47=A0pm, spop...@speedymail.org
(Steve Pope) wrote:
> Pete Fraser <pfra...@covad.net> wrote:
> >I am working on a project where I need to
> >implement 6-th order Butterworth low-pass
> >filters in an FPGA. In some the bandwidth is
> >low relative to the input data rate, whereas
> >others have higher bandwidth. I can use ScopeIIR
> >or Matlab to give me a good idea of coefficient
> >accuracy for any given ratio of bandwidth to
> >input sample rate.
>
> >However, I'm not sure what data-path accuracy
> >I need (for 20-bit input / output accuracy).
> >Is there a rule-of-thumb I can use, or do I just
> >have to simulate the filter with real data and
> >see what gives me low enough noise?
>
> You should simulate the fixed-point filter. =A0When simulating,
> you do not necessarily have to stimulate it with realistic data. =A0I
> often will stimulate the design being tested with bandlimited noise, and
> measure the RMS error of output (relative to the same design, but in full
> floating-point). =A0Plotting the RMS error (in dBc) vs. RMS input level
> gives you a very good idea of the dynamic range of the fixed point
> design.
>
> >I was planning on using biquads, but I'm not sure
> >whether I'm better off with DF1 or DF2 sections.
>
> You can do this, or you can use a lattice topology
> (called "ARMA" in matlab/fdatool), which is the most
> well-behaved topology.
>
> Steve

I recently did just that and concurs with everything Steve said. Most
important figure you need to keep track of is your I/O RMS with the
various quantizations and casts you'd have applied. The places where
casting occurs is of particular importance here and is structure-
related. If your realization is sequential it'd be even harder to sort
out. My final filter was DF2 with a shared biquad core and a memory
trace for states and biquad inputs and outputs. The best performance
for casting you get from convergent. Keep simulating various scenarios
and look at your RMS and play with your structure, quantization, and
castings until you land something satisfactory. Looking at my core's
generics, here are what worked quite well for me:
- core: rolled IIR DF2 SOS
- sample word width: 16
- internal state width: 25
- internal fract width: 15
- coeff word width: 17
- coeff fract width: 15
- output scaling: YES

Regards,
-Momo

On 07/29/2010 12:47 PM, Steve Pope wrote:
> Pete Fraser<p...@covad.net>  wrote:
>
>> I am working on a project where I need to
>> implement 6-th order Butterworth low-pass
>> filters in an FPGA. In some the bandwidth is
>> low relative to the input data rate, whereas
>> others have higher bandwidth. I can use ScopeIIR
>> or Matlab to give me a good idea of coefficient
>> accuracy for any given ratio of bandwidth to
>> input sample rate.
>>
>> However, I'm not sure what data-path accuracy
>> I need (for 20-bit input / output accuracy).
>> Is there a rule-of-thumb I can use, or do I just
>> have to simulate the filter with real data and
>> see what gives me low enough noise?
>
> You should simulate the fixed-point filter.  When simulating,
> you do not necessarily have to stimulate it with realistic data.  I
> often will stimulate the design being tested with bandlimited noise, and
> measure the RMS error of output (relative to the same design, but in full
> floating-point).  Plotting the RMS error (in dBc) vs. RMS input level
> gives you a very good idea of the dynamic range of the fixed point
> design.
>
>> I was planning on using biquads, but I'm not sure
>> whether I'm better off with DF1 or DF2 sections.
>
> You can do this, or you can use a lattice topology
> (called "ARMA" in matlab/fdatool), which is the most
> well-behaved topology.
>
> Steve

I did a quick search on "digital lattice filter" and didn't come up with 
any really coherent discussion.  There was lots of stuff about how to 
use this or that lattice filter in this or that specialized application, 
but not "this is DF1, this is DF2, this is a digital lattice filter...".

Got any references?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

On 07/29/2010 12:23 PM, Pete Fraser wrote:
> I am working on a project where I need to
> implement 6-th order Butterworth low-pass
> filters in an FPGA. In some the bandwidth is
> low relative to the input data rate, whereas
> others have higher bandwidth. I can use ScopeIIR
> or Matlab to give me a good idea of coefficient
> accuracy for any given ratio of bandwidth to
> input sample rate.
>
> However, I'm not sure what data-path accuracy
> I need (for 20-bit input / output accuracy).
> Is there a rule-of-thumb I can use, or do I just
> have to simulate the filter with real data and
> see what gives me low enough noise?
>
> I was planning on using biquads, but I'm not sure
> whether I'm better off with DF1 or DF2 sections.

What Vladimir and Steve said.  If you want to know for sure, make a 
block diagram of the filter, put in summing junctions for the 
quantizers, then find the transfer function from that summing junction 
to the output.  Do a Bode plot, and figure that your output noise will 
be your quantization noise times the worst-case gain.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Tim Wescott  <t...@seemywebsite.com> wrote:

>I did a quick search on "digital lattice filter" and didn't come up with 
>any really coherent discussion.  There was lots of stuff about how to 
>use this or that lattice filter in this or that specialized application, 
>but not "this is DF1, this is DF2, this is a digital lattice filter...".

>Got any references?

A classical description of lattice filters is in Rabiner and
Schafer, where they are called "lattice filters".  But in
the Mathworks world, they are called "ARMA filters", or
sometimes "lattice ARMA" filters.

Something like the Mathworks Filter Design Toolbox has a passable
explanation of this topology.

Steve

On 30 Jul, 01:42, Tim Wescott
<t...@seemywebsite.com> wrote:
> On 07/29/2010 12:47 PM, Steve Pope wrote:
>
>
>
>
>
> > Pete Fraser<pfra...@covad.net> =A0wrote:
>
> >> I am working on a project where I need to
> >> implement 6-th order Butterworth low-pass
> >> filters in an FPGA. In some the bandwidth is
> >> low relative to the input data rate, whereas
> >> others have higher bandwidth. I can use ScopeIIR
> >> or Matlab to give me a good idea of coefficient
> >> accuracy for any given ratio of bandwidth to
> >> input sample rate.
>
> >> However, I'm not sure what data-path accuracy
> >> I need (for 20-bit input / output accuracy).
> >> Is there a rule-of-thumb I can use, or do I just
> >> have to simulate the filter with real data and
> >> see what gives me low enough noise?
>
> > You should simulate the fixed-point filter. =A0When simulating,
> > you do not necessarily have to stimulate it with realistic data. =A0I
> > often will stimulate the design being tested with bandlimited noise, an=
d
> > measure the RMS error of output (relative to the same design, but in fu=
ll
> > floating-point). =A0Plotting the RMS error (in dBc) vs. RMS input level
> > gives you a very good idea of the dynamic range of the fixed point
> > design.
>
> >> I was planning on using biquads, but I'm not sure
> >> whether I'm better off with DF1 or DF2 sections.
>
> > You can do this, or you can use a lattice topology
> > (called "ARMA" in matlab/fdatool), which is the most
> > well-behaved topology.
>
> > Steve
>
> I did a quick search on "digital lattice filter" and didn't come up with
> any really coherent discussion. =A0There was lots of stuff about how to
> use this or that lattice filter in this or that specialized application,
> but not "this is DF1, this is DF2, this is a digital lattice filter...".
>
> Got any references?

These filters are treated in medium / advanced level
DSP books, like Proakis & Manolakis. Don't think the
term 'lattice filter' is too common, though; rather
'lattice structure' or 'lattice ladder structure'.

I am not sure they are worth a general discussion:
The problem is that the lattice structure fuses both
the FIR and its IIR inverse, so if the FIR has zeros on
or outside the unit circle, the computations blow up.

It makes a lot of sense keeping those disussion on a
need to know basis.

Rune

Rune Allnor  <a...@tele.ntnu.no> wrote:

>On 30 Jul, 01:42, Tim Wescott <t...@seemywebsite.com> wrote:

>> On 07/29/2010 12:47 PM, Steve Pope wrote:

>> > You can do this, or you can use a lattice topology

>> I did a quick search on "digital lattice filter" and didn't come up
with
>> any really coherent discussion.  There was lots of stuff about how to
>> use this or that lattice filter in this or that specialized application,
>> but not "this is DF1, this is DF2, this is a digital lattice
filter...".

>> Got any references?

>These filters are treated in medium / advanced level
>DSP books, like Proakis & Manolakis. Don't think the
>term 'lattice filter' is too common, though; rather
>'lattice structure' or 'lattice ladder structure'.

>I am not sure they are worth a general discussion:
>The problem is that the lattice structure fuses both
>the FIR and its IIR inverse, so if the FIR has zeros on
>or outside the unit circle, the computations blow up.

I do not think this is a problem in practice.  The FIR
form of any topology is stable; the IIR form of the lattice
topology is unconditionally stable if the coefficients are
in the range (-1,1) and you are using saturating arithmetic.
This latter fact makes them very useful in implementation,
because (almost) any IIR filter you would want to implement
satisfies this constraint.

>It makes a lot of sense keeping those disussion on a
>need to know basis.

Just FYI, the lattice topology is my first-line choice
for implementing a typical IIR such as the OP's Butterworth.
I only go to something else if the lattice topology it
too costly (it does take 3*N+1 multiplies to implement
a N-pole, N-zero filter. But often the multipliers are
somewhat lower precision than in other topologies;
the coefficients tend to be pretty insensitive.)
I have used these filters many, many times because the
design time is really short because you don't have
to angst over whether you've chosen a well-behaved structure.

Steve