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Comp.Arch.FPGA | Differences between Verilog versions

There are 4 messages in this thread.

You are currently looking at messages 0 to 4.

Differences between Verilog versions - Giorgos Tzampanakis - 2010-07-31 21:06:00

Where can I find a listing of the features that
were added to
Verilog in the 2001 version, and then of the ones added in
SystemVerilog?
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Re: Differences between Verilog versions - Jonathan Bromley - 2010-08-01 14:56:00

On Sun, 1 Aug 2010 01:06:16 +0000 (UTC), Giorgos
Tzampanakis wrote:

>Where can I find a listing of the features that were added to
>Verilog in the 2001 version, and then of the ones added in
>SystemVerilog?

It's surprisingly hard to extract that information.  IEEE 
standards conventions strongly discourage the provision 
of such "delta" information - the standard is the standard,
that's it - and although the information can be plucked 
from reference guides and suchlike it's still not easy.
For example, at one point the Doulos Verilog Golden
Reference Guide highlighted V-2001 features, but in
recent years that disappeared (as V-2001 became the
norm everywhere) and the highlights are now for 
newer stuff.

There's a bit of me that asks "why do you want to
know", I suppose.  If you need a feature, use it 
in your code and then, if the compiler whines at 
you, change the compiler switches to use the
newer version!  Indeed, one good thing about all
this is that each new version has carefully 
preserved back-compatibility with earlier versions,
so in general you lose very little by setting
your tools for the latest version they support.

The obvious drawback to that is that each new
version introduced new keywords. I can't give
you a definitive list, but in V-2001 you 
certainly got "generate", "genvar", "signed",
"automatic" and "endgenerate"; if you try to compile 
legal V-1995 code that uses these names as identifiers,
of course any V-2001 tool will complain.  That's
why the "begin_keywords" and "end_keywords" compiler
directives were added to SystemVerilog: they
don't change the compiler's behaviour, but
they disable recognition of certain keywords
for just that reason.

SystemVerilog adds so much new stuff that it's 
almost a new language that happens to include
Verilog as a subset, so I don't think it's
terribly helpful to list the deltas there.

V-2001 versus V-1995 was not so bad.  My 
non-definitive checklist of changes is...

- So-called "ANSI-style" port lists in which
  the whole declaration of a port goes in the
  port list.  In V-95 the port list was merely
  a list of names, and the ports got declared
  elsewhere in the code.
- Signed reg and wire declarations, and related
  enhancements: signed literal numbers like 2'sb01,
  $signed and $unsigned conversions, <<< and >>>
  signedness-respecting shift operators.
- Variable initialization as part of its 
  declaration:
    reg [7:0] myVar = 8'd35;
  defined to be shorthand for the declaration and
  an initial block that does the initialization
- Multi-dimensional arrays of vectors like
    wire [7:0] array2D_of_byte [0:5] [0:9];
  (but not multi-dimensional ports!)
- Generate if/case/for and genvar
- Localparam, and the parameter port list
    module M #(parameter N=5) (input clk, ...);
- always @*
- comma-separated sensitivity lists (as an option
  to the "or" operator)
- standardization of the C-style file I/O functions
  such as $fscanf; single-channel file descriptors
  to support read files
- task automatic, function automatic
- Context-determined width for unsized literals
  whose first bit is X or Z
- Standardized C-language algorithms for the
  random number generator system functions

In all of this, the only back-compatibility issues
I know about going from V-95 to V-2001 are:
- Changed behaviour of 'bz, 'bx when assigned to a
  target with more than 32 bits (but it was almost 
  certainly a bug in V-95 code anyway)
- Old-style multi-channel file descriptors now support
  only a maximum of 30 open files, not 31, because
  the MSB of a file descriptor is now a flag to 
  mark new-style single-channel descriptors

I've no doubt that I will have missed one or two 
changes, but that's not a bad list to get you started.

cheers
-- 
Jonathan Bromley

Re: Differences between Verilog versions - 2010-08-04 21:35:00

Regarding Jonathan's comment about new keywords
added in later
revisions of the language: that is one thing that is actually well-
documented for each version.  The specification of the `begin_keywords
directive lists the keywords that were reserved in each revision.

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Re: Differences between Verilog versions - Ramesh - 2010-08-26 17:09:00

On Aug 1, 11:56=A0am, Jonathan Bromley
<s...@oxfordbromley.plus.com>
wrote:
> On Sun, 1 Aug 2010 01:06:16 +0000 (UTC), Giorgos Tzampanakis wrote:
> >Where can I find a listing of the features that were added to
> >Verilog in the 2001 version, and then of the ones added in
> >SystemVerilog?
>

Verilog 95 to 2001 differences are summarized in
http://www.sutherland-hdl.com/papers/2001-SNUG-paper_Verilog-2000_standard.=
pdf
.

Verilog 2001 to SystemVerilog is described in the overview section of
the SV LRM 1800-2005 (page 15). The SV LRM only describes the SV
extensions to Verilog 2001.
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