Hello All,

I am writing this to seek your guidance in knowing the possiblemethods/procedures to verify the analytical SEU estmiates for an FPGAdesigns.  To my understanding the way to go about it is beam testing orlaser testing. The fault injection methods don't seem to me prudent in thiscase as we are checking the estimate of soft errors in an FPGA design andnot verifying a mitigating methodology ?

My second query is related to the method of estimating SEU rate in XilinxFPGAs. I am utilizing the knowledge obtained from XDL and FPGA Editor tomake an estimate of configuration bits used by my design. The problem I amencountering is how to estimate total configuration bits in the nets thatare related to "pips". 

for example it is true that a pip connecting two nodes of a switch willrequire only one configuration bit, but at the same time each node of theswitch is connected to several other nodes. Hence potentially the net mayget connected to an irrelevant node (erroneously) due to SEU. And thisleads to me the question that what should I do to cope such a scenario inan effort to provide realistic estimate of configuration bits ?

Of course what I am doing is with publicly available information fromXilinx and hence it should not cause any legal hitch.

Your recommendations would be highly appreciated.

Rafay  


	   
					
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