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Comp.Arch.FPGA | Text compression Huffman Encoder and Decoder
There are 15 messages in this thread.
You are currently looking at messages 0 to 10.
Text compression Huffman Encoder and Decoder - kude - 2010-08-24 07:39:00
Hi all, I am working on text Huffman Encoder and Decoder to be implemented onFPGA. and here are things which are not clear for me. 1.Will the binary tree be constructed by software and then the coded databe taken and VHDL coded OR can I construct the Binary tree using VHDL? andI need some hint. kude --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: Text compression Huffman Encoder and Decoder - David Brown - 2010-08-24 09:23:00
On 24/08/2010 13:39, kude wrote: > Hi all, > I am working on text Huffman Encoder and Decoder to be implemented on > FPGA. > and here are things which are not clear for me. > 1.Will the binary tree be constructed by software and then the coded data > be taken and VHDL coded OR can I construct the Binary tree using VHDL? and > I need some hint. > That's up to you. If you construct the tree in software and generate the VHDL from a fixed tree, the hardware will be a lot easier. But then you have a fixed tree - it will only be efficient for encoding data that matches that tree.
Re: Text compression Huffman Encoder and Decoder - RCIngham - 2010-08-24 10:59:00
Very old hat... http://www.xilinx.com/support/documentation/application_notes/xapp616.pdf --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: Text compression Huffman Encoder and Decoder - kude - 2010-08-24 12:03:00
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the codeddata >> be taken and VHDL coded OR can I construct the Binary tree using VHDL?and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using theVHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: Text compression Huffman Encoder and Decoder - kude - 2010-08-24 12:07:00
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the codeddata >> be taken and VHDL coded OR can I construct the Binary tree using VHDL?and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using theVHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.com
Re: Text compression Huffman Encoder and Decoder - kude - 2010-08-24 12:12:00
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the codeddata >> be taken and VHDL coded OR can I construct the Binary tree using VHDL?and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using theVHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: Text compression Huffman Encoder and Decoder - kude - 2010-08-24 12:22:00
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the codeddata >> be taken and VHDL coded OR can I construct the Binary tree using VHDL?and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using theVHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.com
Re: Text compression Huffman Encoder and Decoder - Tim Wescott - 2010-08-24 12:32:00
On 08/24/2010 09:03 AM, kude wrote: >> On 24/08/2010 13:39, kude wrote: >>> Hi all, >>> I am working on text Huffman Encoder and Decoder to be implemented on >>> FPGA. >>> and here are things which are not clear for me. >>> 1.Will the binary tree be constructed by software and then the coded > data >>> be taken and VHDL coded OR can I construct the Binary tree using VHDL? > and >>> I need some hint. >>> >> >> That's up to you. If you construct the tree in software and generate >> the VHDL from a fixed tree, the hardware will be a lot easier. But then >> you have a fixed tree - it will only be efficient for encoding data that >> matches that tree. >> > > @David Brown,ok but what if I want to construct the tree using the > VHDL,where shall I start? http://www.altavista.com/web/results?fr=altavista&itag=ody&q=Huffman+Encoding&; kgs=0&kls=0 > And what logic units will I need ? Who knows? Finish your project and you can tell us. If you're lucky there's a book out there on implementing data compression in logic; I suspect, however, that what there is are a lot of very specific, narrowly focused materials on specific methods (i.e. "Implementing Video Compression in Digital Hardware"). And that's if you're lucky -- if you're not lucky then there are 10 companies out there that have each learned how to do it, and no one wants to tell anyone else how it's done. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Re: Text compression Huffman Encoder and Decoder - kude - 2010-08-24 12:48:00
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the codeddata >> be taken and VHDL coded OR can I construct the Binary tree using VHDL?and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using theVHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.com______________________________
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Re: Text compression Huffman Encoder and Decoder - glen herrmannsfeldt - 2010-08-24 13:22:00
kude <tadmas09@n_o_s_p_a_m.gmail.com> wrote: > I am working on text Huffman Encoder and Decoder to be > implemented on FPGA. I recommend looking at the literature on systolic arrays. I am not so sure, but I believe that works well for many compression algorithms. Remember that you are building hardware, and the size must be specified before synthesis. You can't do dynamic allocation as in many programming languages. -- glen______________________________
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