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Comp.Arch.FPGA | How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board

There are 12 messages in this thread.

You are currently looking at messages 0 to 10.

How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Pratap - 2011-03-25 20:59:00

Hi,
I want to delay a signal precisely by taking out the signal from the
FPGA so that it can be fed to another chip which can control the delay
through that. I want to feed this delayed signal back to the FPGA by
inputting that signal through another pin on the Xilinx Virtex II Pro
board. I am using the EXT_CLK_P and EXT_CLK_N pins for inputting the
desired signals. The signal to be delayed is fed to the pin EXT_CLK_P
by installing SMA connectors at those points. I have also installed
separate connectors at EXT_CLK_N, MGT_TXP and MGT_TXN. But I am not
able to route the signals as I get the following error while mapping.

Using target part "2vp30ff896-7".
Mapping design into LUTs...
Running directed packing...
ERROR:Pack:1107 - Unable to combine the following symbols into a
single IOB
   component:
   	BUF symbol "inp_for_TI_chip_OBUF" (Output Signal =
inp_for_TI_chip)
   	PAD symbol "inp_for_TI_chip" (Pad Signal = inp_for_TI_chip)
   Each of the following constraints specifies an illegal physical
site for a
   component of type IOB:
   	Symbol "inp_for_TI_chip" (LOC=A6)
   Please correct the constraints accordingly.

The motivation behind using the SMA connectors for the connectivity is
to have good signal shape of the input square wave signals, by which
the delays can be precisely maintained. I have also tried connect the
output from the FPGA pin for the external delay controller and also
the input signal from the controller to the chip through other Non-SMA
type pins in J5 or J6 connectors. But even doing that doesn't solve my
purpose, as I don't get any thing signal reaching at those points.
Surprisingly, only when I connect those signals intended to be fed to
the external delay controller chip to the externally non-available
pins MGT_CLK_P and MGT_CLK_N, I get all the signals toggling, but my
purpose of routing the signals through the external chip is not
solved.
Can anybody help me understand, why this connection to MGT_CLK_P and
MGT_CLK_N for the stuff to work and how those are hooked upto the
system? How can I solve my purpose of taking the signals fed to
EXT_CLK_P and EXT_CLK_N SMA connectors from the Virtex II Pro board
and route it through another chip.
Looking forward to some helpful suggestions,
Thanks in advance,
Pratap
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Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Ed McGettigan - 2011-03-26 00:04:00

On Mar 25, 5:59=A0pm, Pratap
<pratap.i...@gmail.com> wrote:
> Hi,
> I want to delay a signal precisely by taking out the signal from the
> FPGA so that it can be fed to another chip which can control the delay
> through that. I want to feed this delayed signal back to the FPGA by
> inputting that signal through another pin on the Xilinx Virtex II Pro
> board. I am using the EXT_CLK_P and EXT_CLK_N pins for inputting the
> desired signals. The signal to be delayed is fed to the pin EXT_CLK_P
> by installing SMA connectors at those points. I have also installed
> separate connectors at EXT_CLK_N, MGT_TXP and MGT_TXN. But I am not
> able to route the signals as I get the following error while mapping.
>
> Using target part "2vp30ff896-7".
> Mapping design into LUTs...
> Running directed packing...
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
> =A0 =A0component:
> =A0 =A0 =A0 =A0 BUF symbol "inp_for_TI_chip_OBUF" (Output Signal =3D
> inp_for_TI_chip)
> =A0 =A0 =A0 =A0 PAD symbol "inp_for_TI_chip" (Pad Signal =3D inp_for_TI_c=
hip)
> =A0 =A0Each of the following constraints specifies an illegal physical
> site for a
> =A0 =A0component of type IOB:
> =A0 =A0 =A0 =A0 Symbol "inp_for_TI_chip" (LOC=3DA6)
> =A0 =A0Please correct the constraints accordingly.
>
> The motivation behind using the SMA connectors for the connectivity is
> to have good signal shape of the input square wave signals, by which
> the delays can be precisely maintained. I have also tried connect the
> output from the FPGA pin for the external delay controller and also
> the input signal from the controller to the chip through other Non-SMA
> type pins in J5 or J6 connectors. But even doing that doesn't solve my
> purpose, as I don't get any thing signal reaching at those points.
> Surprisingly, only when I connect those signals intended to be fed to
> the external delay controller chip to the externally non-available
> pins MGT_CLK_P and MGT_CLK_N, I get all the signals toggling, but my
> purpose of routing the signals through the external chip is not
> solved.
> Can anybody help me understand, why this connection to MGT_CLK_P and
> MGT_CLK_N for the stuff to work and how those are hooked upto the
> system? How can I solve my purpose of taking the signals fed to
> EXT_CLK_P and EXT_CLK_N SMA connectors from the Virtex II Pro board
> and route it through another chip.
> Looking forward to some helpful suggestions,
> Thanks in advance,
> Pratap

The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
by the MGTs.  In the Virtex-II Pro FPGA family the MGT reference clock
pins were normal I/Os that had extra dedicated routing to the MGTs.

Are you using a Xilinx board?  If so which one is it?

What are the IO location constraints that you are using for the output
and input paths?

Ed McGettigan
--
Xilinx Inc.

Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Pratap - 2011-03-26 10:53:00

> The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
> by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference clock
> pins were normal I/Os that had extra dedicated routing to the MGTs.
>
> Are you using a Xilinx board? =A0If so which one is it?
>
> What are the IO location constraints that you are using for the output
> and input paths?
>
> Ed McGettigan
> --
> Xilinx Inc.

Hello,
I am using the Virtex II Pro development board for my project.
I am pasting all the IO constraints written to the ucf file.
The signals to take out and then feed in are "inp_for_TI_chip" and
"op_from_TI_chip" respectively.

NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25;
#LEFT P/B

NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25;
#EXTERNAL_CLOCK_P

NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25;
#EXTERNAL_CLOCK_N

NET "op_from_TI_chip"  LOC =3D "A6" | IOSTANDARD =3D LVCMOS25;
#MGT_TXP

NET "inp_for_TI_chip"  LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D
FAST | DRIVE =3D 8 ;
#MGT_TXN

NET "ti_delay_chip_cntl"  LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D
FAST | DRIVE =3D 8 ;
#J5-11

NET "dir_fine_delay"  LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D FAS=
T
| DRIVE =3D 8 ;
#J5-15

NET "board_in1"  LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
FAST |
DRIVE =3D 8 ;
#J6-27

NET "board_in2"  LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
FAST |
DRIVE =3D 8 ;
#J6-35

NET "cleaned_clk1"  LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
FAST =
|
DRIVE =3D 8 ;
#J5-31

NET "cleaned_clk2"  LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
FAST =
|
DRIVE =3D 8 ;
#J5-39

NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
SLOW |
DRIVE =3D 12 ;
NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
SLOW |
DRIVE =3D 12 ;
NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
SLOW |
DRIVE =3D 12 ;
NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D
SLOW |
DRIVE =3D 12 ;


Thanks,
Pratap
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Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Ed McGettigan - 2011-03-26 20:32:00

On Mar 26, 7:53=A0am, Pratap
<pratap.i...@gmail.com> wrote:
> > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
> > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference cloc=
k
> > pins were normal I/Os that had extra dedicated routing to the MGTs.
>
> > Are you using a Xilinx board? =A0If so which one is it?
>
> > What are the IO location constraints that you are using for the output
> > and input paths?
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Hello,
> I am using the Virtex II Pro development board for my project.
> I am pasting all the IO constraints written to the ucf file.
> The signals to take out and then feed in are "inp_for_TI_chip" and
> "op_from_TI_chip" respectively.
>
> NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25;
> #LEFT P/B
>
> NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25;
> #EXTERNAL_CLOCK_P
>
> NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25;
> #EXTERNAL_CLOCK_N
>
> NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25;
> #MGT_TXP
>
> NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 |
SLEW =
=3D
> FAST | DRIVE =3D 8 ;
> #MGT_TXN
>
> NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D
LVCMOS25 | SLEW=
 =3D
> FAST | DRIVE =3D 8 ;
> #J5-11
>
> NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D=
 FAST
> | DRIVE =3D 8 ;
> #J5-15
>
> NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D FAS=
T |
> DRIVE =3D 8 ;
> #J6-27
>
> NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D FAST=
 |
> DRIVE =3D 8 ;
> #J6-35
>
> NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D F=
AST |
> DRIVE =3D 8 ;
> #J5-31
>
> NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D F=
AST |
> DRIVE =3D 8 ;
> #J5-39
>
> NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
>
> Thanks,
> Pratap

> I am using the Virtex II Pro development board for my project.

This is about as useful as saying that your computer has an Intel ATX
motherboard.  Who made the board, and what is the model number?

Ed McGettigan
--
Xilinx Inc.
______________________________
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Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Ed McGettigan - 2011-03-26 21:39:00

On Mar 26, 7:53=A0am, Pratap
<pratap.i...@gmail.com> wrote:
> > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
> > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference cloc=
k
> > pins were normal I/Os that had extra dedicated routing to the MGTs.
>
> > Are you using a Xilinx board? =A0If so which one is it?
>
> > What are the IO location constraints that you are using for the output
> > and input paths?
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Hello,
> I am using the Virtex II Pro development board for my project.
> I am pasting all the IO constraints written to the ucf file.
> The signals to take out and then feed in are "inp_for_TI_chip" and
> "op_from_TI_chip" respectively.
>
> NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25;
> #LEFT P/B
>
> NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25;
> #EXTERNAL_CLOCK_P
>
> NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25;
> #EXTERNAL_CLOCK_N
>
> NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25;
> #MGT_TXP
>
> NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 |
SLEW =
=3D
> FAST | DRIVE =3D 8 ;
> #MGT_TXN
>
> NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D
LVCMOS25 | SLEW=
 =3D
> FAST | DRIVE =3D 8 ;
> #J5-11
>
> NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D=
 FAST
> | DRIVE =3D 8 ;
> #J5-15
>
> NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D FAS=
T |
> DRIVE =3D 8 ;
> #J6-27
>
> NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D FAST=
 |
> DRIVE =3D 8 ;
> #J6-35
>
> NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D F=
AST |
> DRIVE =3D 8 ;
> #J5-31
>
> NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D F=
AST |
> DRIVE =3D 8 ;
> #J5-39
>
> NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
> NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D SLOW |
> DRIVE =3D 12 ;
>
> Thanks,
> Pratap

The UCF file constraints have regular IO location assignments to A7
and A6 which are the MGT TXP/TXN pins.  These locations are not valid
for anything other than MGT TXP/TXN pins and your original post
indicated that you had changed these to other locations and it worked.

I'm confused.  What exactly is your question or problem?

Ed McGettigan
--
Xilinx Inc.
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Pratap - 2011-03-26 23:41:00

On Mar 27, 6:39=A0am, Ed McGettigan
<ed.mcgetti...@xilinx.com> wrote:
> On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote:
>
>
>
> > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used
> > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference cl=
ock
> > > pins were normal I/Os that had extra dedicated routing to the MGTs.
>
> > > Are you using a Xilinx board? =A0If so which one is it?
>
> > > What are the IO location constraints that you are using for the outpu=
t
> > > and input paths?
>
> > > Ed McGettigan
> > > --
> > > Xilinx Inc.
>
> > Hello,
> > I am using the Virtex II Pro development board for my project.
> > I am pasting all the IO constraints written to the ucf file.
> > The signals to take out and then feed in are "inp_for_TI_chip" and
> > "op_from_TI_chip" respectively.
>
> > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25;
> > #LEFT P/B
>
> > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25;
> > #EXTERNAL_CLOCK_P
>
> > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25;
> > #EXTERNAL_CLOCK_N
>
> > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D
LVCMOS25;
> > #MGT_TXP
>
> > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D
> > FAST | DRIVE =3D 8 ;
> > #MGT_TXN
>
> > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D
LVCMOS25 | SL=
EW =3D
> > FAST | DRIVE =3D 8 ;
> > #J5-11
>
> > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST
> > | DRIVE =3D 8 ;
> > #J5-15
>
> > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D F=
AST |
> > DRIVE =3D 8 ;
> > #J6-27
>
> > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D FA=
ST |
> > DRIVE =3D 8 ;
> > #J6-35
>
> > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25
| SLEW =3D=
 FAST |
> > DRIVE =3D 8 ;
> > #J5-31
>
> > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25
| SLEW =3D=
 FAST |
> > DRIVE =3D 8 ;
> > #J5-39
>
> > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D SLOW=
 |
> > DRIVE =3D 12 ;
> > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D SLOW=
 |
> > DRIVE =3D 12 ;
> > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D SLOW=
 |
> > DRIVE =3D 12 ;
> > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 |
SLEW =3D SLOW=
 |
> > DRIVE =3D 12 ;
>
> > Thanks,
> > Pratap
>
> The UCF file constraints have regular IO location assignments to A7
> and A6 which are the MGT TXP/TXN pins. =A0These locations are not valid
> for anything other than MGT TXP/TXN pins and your original post
> indicated that you had changed these to other locations and it worked.
>
> I'm confused. =A0What exactly is your question or problem?
>
> Ed McGettigan
> --
> Xilinx Inc.


Yes,
This is the ucf file that is not working. The ucf file that ensures
that there is toggling at all the signal ports is as follows.

NET "op_from_TI_chip"  LOC =3D "F16" | IOSTANDARD =3D LVCMOS25;
#MGT_CLK_P

NET "inp_for_TI_chip"  LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SLEW
=3D
FAST | DRIVE =3D 8 ;
#MGT_CLK_N

My exact problem is in understanding why in the case when I connect
the pins intended to be interfaced with the other chip to F16 and
G16(The externally non-accessible ports on board) , I get the signals
at the output port. If I connect those two signals to any other  pin,
it doesn't seem to work.
I hope the problem is clear now.

Thanks,
Pratap

Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Ed McGettigan - 2011-03-27 12:39:00

On Mar 26, 8:41=A0pm, Pratap
<pratap.i...@gmail.com> wrote:
> On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote:
>
> > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be us=
ed
> > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference =
clock
> > > > pins were normal I/Os that had extra dedicated routing to the MGTs.
>
> > > > Are you using a Xilinx board? =A0If so which one is it?
>
> > > > What are the IO location constraints that you are using for the out=
put
> > > > and input paths?
>
> > > > Ed McGettigan
> > > > --
> > > > Xilinx Inc.
>
> > > Hello,
> > > I am using the Virtex II Pro development board for my project.
> > > I am pasting all the IO constraints written to the ucf file.
> > > The signals to take out and then feed in are "inp_for_TI_chip"
and
> > > "op_from_TI_chip" respectively.
>
> > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D
LVCMOS25;
> > > #LEFT P/B
>
> > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25;
> > > #EXTERNAL_CLOCK_P
>
> > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D
LVCMOS25;
> > > #EXTERNAL_CLOCK_N
>
> > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D
LVCMOS25;
> > > #MGT_TXP
>
> > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D
LVCMOS25 | SLE=
W =3D
> > > FAST | DRIVE =3D 8 ;
> > > #MGT_TXN
>
> > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD
=3D LVCMOS25 | =
SLEW =3D
> > > FAST | DRIVE =3D 8 ;
> > > #J5-11
>
> > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D
LVCMOS25 | SLEW=
 =3D FAST
> > > | DRIVE =3D 8 ;
> > > #J5-15
>
> > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D=
 FAST |
> > > DRIVE =3D 8 ;
> > > #J6-27
>
> > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
FAST |
> > > DRIVE =3D 8 ;
> > > #J6-35
>
> > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > DRIVE =3D 8 ;
> > > #J5-31
>
> > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > DRIVE =3D 8 ;
> > > #J5-39
>
> > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25
| SLEW =3D SL=
OW |
> > > DRIVE =3D 12 ;
> > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25
| SLEW =3D SL=
OW |
> > > DRIVE =3D 12 ;
> > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25
| SLEW =3D SL=
OW |
> > > DRIVE =3D 12 ;
> > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25
| SLEW =3D SL=
OW |
> > > DRIVE =3D 12 ;
>
> > > Thanks,
> > > Pratap
>
> > The UCF file constraints have regular IO location assignments to A7
> > and A6 which are the MGT TXP/TXN pins. =A0These locations are not valid
> > for anything other than MGT TXP/TXN pins and your original post
> > indicated that you had changed these to other locations and it worked.
>
> > I'm confused. =A0What exactly is your question or problem?
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Yes,
> This is the ucf file that is not working. The ucf file that ensures
> that there is toggling at all the signal ports is as follows.
>
> NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D
LVCMOS25;
> #MGT_CLK_P
>
> NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25
| SLEW =
=3D
> FAST | DRIVE =3D 8 ;
> #MGT_CLK_N
>
> My exact problem is in understanding why in the case when I connect
> the pins intended to be interfaced with the other chip to F16 and
> G16(The externally non-accessible ports on board) , I get the signals
> at the output port. If I connect those two signals to any other =A0pin,
> it doesn't seem to work.
> I hope the problem is clear now.
>
> Thanks,
> Pratap- Hide quoted text -
>
> - Show quoted text -

Sorry, it still isn't very clear and you still haven't identified
which exact board you are using (vendor and model).

As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
anything other that the MGT.  For this device pins F16 and G16 are
regular IO and also MGT reference clock input pins so they can be used
for inputs or outputs.

> If I connect those two signals to any other  pin,
> it doesn't seem to work.

It isn't clear what you mean by any other pin and what doesn't work.

Ed McGettigan
--
Xilinx Inc.

Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Pratap - 2011-03-27 12:57:00

On Mar 27, 9:39=A0pm, Ed McGettigan
<ed.mcgetti...@xilinx.com> wrote:
> On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote:
>
>
>
> > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote:
>
> > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be
=
used
> > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT
referenc=
e clock
> > > > > pins were normal I/Os that had extra dedicated routing to the
MGT=
s.
>
> > > > > Are you using a Xilinx board? =A0If so which one is it?
>
> > > > > What are the IO location constraints that you are using for the
o=
utput
> > > > > and input paths?
>
> > > > > Ed McGettigan
> > > > > --
> > > > > Xilinx Inc.
>
> > > > Hello,
> > > > I am using the Virtex II Pro development board for my project.
> > > > I am pasting all the IO constraints written to the ucf file.
> > > > The signals to take out and then feed in are
"inp_for_TI_chip" and
> > > > "op_from_TI_chip" respectively.
>
> > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D
LVCMOS25;
> > > > #LEFT P/B
>
> > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D
LVCMOS25;
> > > > #EXTERNAL_CLOCK_P
>
> > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D
LVCMOS25;
> > > > #EXTERNAL_CLOCK_N
>
> > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD
=3D LVCMOS25;
> > > > #MGT_TXP
>
> > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD
=3D LVCMOS25 | S=
LEW =3D
> > > > FAST | DRIVE =3D 8 ;
> > > > #MGT_TXN
>
> > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" |
IOSTANDARD =3D LVCMOS25 =
| SLEW =3D
> > > > FAST | DRIVE =3D 8 ;
> > > > #J5-11
>
> > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD
=3D LVCMOS25 | SL=
EW =3D FAST
> > > > | DRIVE =3D 8 ;
> > > > #J5-15
>
> > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J6-27
>
> > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J6-35
>
> > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD
=3D LVCMOS25 | SLEW=
 =3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J5-31
>
> > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD
=3D LVCMOS25 | SLEW=
 =3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J5-39
>
> > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
>
> > > > Thanks,
> > > > Pratap
>
> > > The UCF file constraints have regular IO location assignments to A7
> > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not val=
id
> > > for anything other than MGT TXP/TXN pins and your original post
> > > indicated that you had changed these to other locations and it worked=
.
>
> > > I'm confused. =A0What exactly is your question or problem?
>
> > > Ed McGettigan
> > > --
> > > Xilinx Inc.
>
> > Yes,
> > This is the ucf file that is not working. The ucf file that ensures
> > that there is toggling at all the signal ports is as follows.
>
> > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D
LVCMOS25;
> > #MGT_CLK_P
>
> > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D
LVCMOS25 | SLEW=
 =3D
> > FAST | DRIVE =3D 8 ;
> > #MGT_CLK_N
>
> > My exact problem is in understanding why in the case when I connect
> > the pins intended to be interfaced with the other chip to F16 and
> > G16(The externally non-accessible ports on board) , I get the signals
> > at the output port. If I connect those two signals to any other =A0pin,
> > it doesn't seem to work.
> > I hope the problem is clear now.
>
> > Thanks,
> > Pratap- Hide quoted text -
>
> > - Show quoted text -
>
> Sorry, it still isn't very clear and you still haven't identified
> which exact board you are using (vendor and model).
>
> As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
> anything other that the MGT. =A0For this device pins F16 and G16 are
> regular IO and also MGT reference clock input pins so they can be used
> for inputs or outputs.
>
> > If I connect those two signals to any other =A0pin,
> > it doesn't seem to work.
>
> It isn't clear what you mean by any other pin and what doesn't work.
>
> Ed McGettigan
> --
> Xilinx Inc.

OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap
______________________________
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Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Pratap - 2011-03-27 12:58:00

On Mar 27, 9:39=A0pm, Ed McGettigan
<ed.mcgetti...@xilinx.com> wrote:
> On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote:
>
>
>
> > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote:
>
> > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be
=
used
> > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT
referenc=
e clock
> > > > > pins were normal I/Os that had extra dedicated routing to the
MGT=
s.
>
> > > > > Are you using a Xilinx board? =A0If so which one is it?
>
> > > > > What are the IO location constraints that you are using for the
o=
utput
> > > > > and input paths?
>
> > > > > Ed McGettigan
> > > > > --
> > > > > Xilinx Inc.
>
> > > > Hello,
> > > > I am using the Virtex II Pro development board for my project.
> > > > I am pasting all the IO constraints written to the ucf file.
> > > > The signals to take out and then feed in are
"inp_for_TI_chip" and
> > > > "op_from_TI_chip" respectively.
>
> > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D
LVCMOS25;
> > > > #LEFT P/B
>
> > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D
LVCMOS25;
> > > > #EXTERNAL_CLOCK_P
>
> > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D
LVCMOS25;
> > > > #EXTERNAL_CLOCK_N
>
> > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD
=3D LVCMOS25;
> > > > #MGT_TXP
>
> > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD
=3D LVCMOS25 | S=
LEW =3D
> > > > FAST | DRIVE =3D 8 ;
> > > > #MGT_TXN
>
> > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" |
IOSTANDARD =3D LVCMOS25 =
| SLEW =3D
> > > > FAST | DRIVE =3D 8 ;
> > > > #J5-11
>
> > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD
=3D LVCMOS25 | SL=
EW =3D FAST
> > > > | DRIVE =3D 8 ;
> > > > #J5-15
>
> > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J6-27
>
> > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D
LVCMOS25 | SLEW =
=3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J6-35
>
> > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD
=3D LVCMOS25 | SLEW=
 =3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J5-31
>
> > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD
=3D LVCMOS25 | SLEW=
 =3D FAST |
> > > > DRIVE =3D 8 ;
> > > > #J5-39
>
> > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
> > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D
LVCMOS25 | SLEW =3D =
SLOW |
> > > > DRIVE =3D 12 ;
>
> > > > Thanks,
> > > > Pratap
>
> > > The UCF file constraints have regular IO location assignments to A7
> > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not val=
id
> > > for anything other than MGT TXP/TXN pins and your original post
> > > indicated that you had changed these to other locations and it worked=
.
>
> > > I'm confused. =A0What exactly is your question or problem?
>
> > > Ed McGettigan
> > > --
> > > Xilinx Inc.
>
> > Yes,
> > This is the ucf file that is not working. The ucf file that ensures
> > that there is toggling at all the signal ports is as follows.
>
> > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D
LVCMOS25;
> > #MGT_CLK_P
>
> > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D
LVCMOS25 | SLEW=
 =3D
> > FAST | DRIVE =3D 8 ;
> > #MGT_CLK_N
>
> > My exact problem is in understanding why in the case when I connect
> > the pins intended to be interfaced with the other chip to F16 and
> > G16(The externally non-accessible ports on board) , I get the signals
> > at the output port. If I connect those two signals to any other =A0pin,
> > it doesn't seem to work.
> > I hope the problem is clear now.
>
> > Thanks,
> > Pratap- Hide quoted text -
>
> > - Show quoted text -
>
> Sorry, it still isn't very clear and you still haven't identified
> which exact board you are using (vendor and model).
>
> As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
> anything other that the MGT. =A0For this device pins F16 and G16 are
> regular IO and also MGT reference clock input pins so they can be used
> for inputs or outputs.
>
> > If I connect those two signals to any other =A0pin,
> > it doesn't seem to work.
>
> It isn't clear what you mean by any other pin and what doesn't work.
>
> Ed McGettigan
> --
> Xilinx Inc.

OK.
Let me rephrase the problem.
All I want is, I want to take a signal out of the Xilinx Virtex II Pro
board which is fed to the FPGA pin "G15" (EXT_CLK_N).
If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
through the pin "F15" (EXT_CLK_P), it works absolutely fine.
But when I use both the pins F15 and G15 for two different input
signals, and want to take a delayed version of the signal fed to
"G15", by routing it through any of the pins in the connector series
located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
want to stimulate another chip with this delayed signal coming from
FPGA. The P&R completes without any problem when I use the Pin J37-A14
or any other pin, but when I am checking the signal at that pin by
connecting an oscilloscope probe there, I don't see any signal there.
This is what I mean by, things don't work. Is is there any issue in
taking out the signals connected to F15 or G15 once I use both of
those pins as inputs? If yes, why so and what is the way around?
I hope the question is more straight forward now and thanks for the
patience shown in understanding the issue.
Thanks,
Pratap

Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board - Ed McGettigan - 2011-03-27 17:25:00

On Mar 27, 9:57=A0am, Pratap
<pratap.i...@gmail.com> wrote:
> On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote:
>
> > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com>
wrote:
>
> > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote:
>
> > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can
only b=
e used
> > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT
refere=
nce clock
> > > > > > pins were normal I/Os that had extra dedicated routing to
the M=
GTs.
>
> > > > > > Are you using a Xilinx board? =A0If so which one is it?
>
> > > > > > What are the IO location constraints that you are using for
the=
 output
> > > > > > and input paths?
>
> > > > > > Ed McGettigan
> > > > > > --
> > > > > > Xilinx Inc.
>
> > > > > Hello,
> > > > > I am using the Virtex II Pro development board for my project.
> > > > > I am pasting all the IO constraints written to the ucf file.
> > > > > The signals to take out and then feed in are
"inp_for_TI_chip" an=
d
> > > > > "op_from_TI_chip" respectively.
>
> > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D
LVCMOS25;
> > > > > #LEFT P/B
>
> > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D
LVCMOS25;
> > > > > #EXTERNAL_CLOCK_P
>
> > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D
LVCMOS25;
> > > > > #EXTERNAL_CLOCK_N
>
> > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" |
IOSTANDARD =3D LVCMOS25;
> > > > > #MGT_TXP
>
> > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" |
IOSTANDARD =3D LVCMOS25 |=
 SLEW =3D
> > > > > FAST | DRIVE =3D 8 ;
> > > > > #MGT_TXN
>
> > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" |
IOSTANDARD =3D LVCMOS2=
5 | SLEW =3D
> > > > > FAST | DRIVE =3D 8 ;
> > > > > #J5-11
>
> > > > > NET "dir_fine_delay" =A0LOC =3D "P1" |
IOSTANDARD =3D LVCMOS25 | =
SLEW =3D FAST
> > > > > | DRIVE =3D 8 ;
> > > > > #J5-15
>
> > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD
=3D LVCMOS25 | SLEW=
 =3D FAST |
> > > > > DRIVE =3D 8 ;
> > > > > #J6-27
>
> > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD
=3D LVCMOS25 | SLEW =
=3D FAST |
> > > > > DRIVE =3D 8 ;
> > > > > #J6-35
>
> > > > > NET "cleaned_clk1" =A0LOC =3D "R3" |
IOSTANDARD =3D LVCMOS25 | SL=
EW =3D FAST |
> > > > > DRIVE =3D 8 ;
> > > > > #J5-31
>
> > > > > NET "cleaned_clk2" =A0LOC =3D "U3" |
IOSTANDARD =3D LVCMOS25 | SL=
EW =3D FAST |
> > > > > DRIVE =3D 8 ;
> > > > > #J5-39
>
> > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD
=3D LVCMOS25 | SLEW =
=3D SLOW |
> > > > > DRIVE =3D 12 ;
> > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD
=3D LVCMOS25 | SLEW =
=3D SLOW |
> > > > > DRIVE =3D 12 ;
> > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD
=3D LVCMOS25 | SLEW =
=3D SLOW |
> > > > > DRIVE =3D 12 ;
> > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD
=3D LVCMOS25 | SLEW =
=3D SLOW |
> > > > > DRIVE =3D 12 ;
>
> > > > > Thanks,
> > > > > Pratap
>
> > > > The UCF file constraints have regular IO location assignments to A7
> > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not v=
alid
> > > > for anything other than MGT TXP/TXN pins and your original post
> > > > indicated that you had changed these to other locations and it work=
ed.
>
> > > > I'm confused. =A0What exactly is your question or problem?
>
> > > > Ed McGettigan
> > > > --
> > > > Xilinx Inc.
>
> > > Yes,
> > > This is the ucf file that is not working. The ucf file that ensures
> > > that there is toggling at all the signal ports is as follows.
>
> > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D
LVCMOS25;
> > > #MGT_CLK_P
>
> > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D
LVCMOS25 | SL=
EW =3D
> > > FAST | DRIVE =3D 8 ;
> > > #MGT_CLK_N
>
> > > My exact problem is in understanding why in the case when I connect
> > > the pins intended to be interfaced with the other chip to F16 and
> > > G16(The externally non-accessible ports on board) , I get the signals
> > > at the output port. If I connect those two signals to any other =A0pi=
n,
> > > it doesn't seem to work.
> > > I hope the problem is clear now.
>
> > > Thanks,
> > > Pratap- Hide quoted text -
>
> > > - Show quoted text -
>
> > Sorry, it still isn't very clear and you still haven't identified
> > which exact board you are using (vendor and model).
>
> > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for
> > anything other that the MGT. =A0For this device pins F16 and G16 are
> > regular IO and also MGT reference clock input pins so they can be used
> > for inputs or outputs.
>
> > > If I connect those two signals to any other =A0pin,
> > > it doesn't seem to work.
>
> > It isn't clear what you mean by any other pin and what doesn't work.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> OK.
> Let me rephrase the problem.
> All I want is, I want to take a signal out of the Xilinx Virtex II Pro
> board which is fed to the FPGA pin "G15" (EXT_CLK_N).
> If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA
> through the pin "F15" (EXT_CLK_P), it works absolutely fine.
> But when I use both the pins F15 and G15 for two different input
> signals, and want to take a delayed version of the signal fed to
> "G15", by routing it through any of the pins in the connector series
> located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I
> want to stimulate another chip with this delayed signal coming from
> FPGA. The P&R completes without any problem when I use the Pin J37-A14
> or any other pin, but when I am checking the signal at that pin by
> connecting an oscilloscope probe there, I don't see any signal there.
> This is what I mean by, things don't work. Is is there any issue in
> taking out the signals connected to F15 or G15 once I use both of
> those pins as inputs? If yes, why so and what is the way around?
> I hope the question is more straight forward now and thanks for the
> patience shown in understanding the issue.
> Thanks,
> Pratap- Hide quoted text -
>
> - Show quoted text -

Pratap,

You still haven't said what board you are using. who made the board
and what is the model name?  This is very important information.

Ed McGettigan
--
Xilinx Inc.
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