Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA | Instantiation of an EDF netlist within a Verilog top RTL
There are 3 messages in this thread.
You are currently looking at messages 0 to 3.
Instantiation of an EDF netlist within a Verilog top RTL - rahul_fpga - 2011-05-26 15:22:00
Hello Guys, I am working with Synplify Pro. I have a RTL wrapper in Verilog where amodule is instantiated. But this module is available as an EDF netlist. Howcan I include this EDF netlist in my Synplify project so that it can beintegrated with the wrapper RTL without any compilation error? Best regards, Rahul --------------------------------------- Posted through http://www.FPGARelated.com
Re: Instantiation of an EDF netlist within a Verilog top RTL - maxascent - 2011-05-27 04:05:00
>Hello Guys, > >I am working with Synplify Pro. I have a RTL wrapper in Verilog where a >module is instantiated. But this module is available as an EDF netlist.How >can I include this EDF netlist in my Synplify project so that it can be >integrated with the wrapper RTL without any compilation error? > >Best regards, >Rahul > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > Just add a blackbox synthesis directive to the wrapper and everything willbe fine. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Re: Instantiation of an EDF netlist within a Verilog top RTL - shyam - 2011-05-30 03:25:00
On May 27, 1:05=A0pm, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > >Hello Guys, > > >I am working with Synplify Pro. I have a RTL wrapper in Verilog where a > >module is instantiated. But this module is available as an EDF netlist. > How > >can I include this EDF netlist in my Synplify project so that it can be > >integrated with the wrapper RTL without any compilation error? > > >Best regards, > >Rahul > > >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > >Posted throughhttp://www.FPGARelated.com > > Just add a blackbox synthesis directive to the wrapper and everything wil= l > be fine. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Additionally, IO insertion should be disabled when the EDIF netlist is generated. If IO insertion isn't disabled, Synplify Pro treats the inputs and outputs on the RTL used for edif netlist as IOs and instantiates IO pads on it. Thanks Shyam