Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Introduction to FPGA Technology
Muhammad Yasir lays out a concise primer on FPGA fundamentals, covering internal architecture, vendors, and practical selection criteria. He explains how logic cells, LUTs, flip-flops, carry chains, block RAM, and I/O blocks combine to determine capacity and performance. This friendly overview shows why FPGAs beat ASICs for low-volume or rapidly changing designs, and how to match device resources to your application needs.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
