## MyHDL Interface Example

January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

## MyHDL FPGA Tutorial I (LED Strobe)

January 31, 20126 comments

Last updated 05-Nov-2015

Introduction

## MyHDL Interface Example

January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

## A Bit Bucket had Holes

July 28, 20101 comment

Couple months ago I wrote a quick little blog about a company called Tabula.  Tabula has a virtual 3D approach to achieving higher logic density in an FPGA.  See the previous blog for more information.

Along similar lines was another company called TierLogic which actually had multiple physical layers.  I was impressed with the Tabula approach and claims.  Along the same lines the TierLogic technology looked promising as well.  But, EE Times has reported that...