MyHDL FPGA Tutorial II (Audio Echo)
IntroductionThis tutorial will walk through an audio echo that can be implemented on an FPGA development board. This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial. This project will require an FPGA board with an audio codec and the interface logic to the audio codec.
Review the Previous TutorialThe previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board. In that tutorial we introduced the basics of a MyHDL module....
Are you kidding me?
If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost. The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows). A quote from the blog.
... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...
C/C++/SystemC, are you kidding...
Grandiose Delusions
Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools. In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL. For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.
Many design languages have relied on that first big...
State Machine ‘v’ Micro in a FPGA
Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.
We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...
Developing FPGA-DSP IP with Python
This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.
Developing FPGA-DSP IP with Python / MyHDLUsing Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...
MyHDL FPGA Tutorial II (Audio Echo)
IntroductionThis tutorial will walk through an audio echo that can be implemented on an FPGA development board. This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial. This project will require an FPGA board with an audio codec and the interface logic to the audio codec.
Review the Previous TutorialThe previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board. In that tutorial we introduced the basics of a MyHDL module....
Cutting a Path Forward
IntroductionAs a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.
My day job is as a professional software developer: Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.
By night, however, I've been working on my...
MyHDL synthesis: from browser to FPGA in five seconds
When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.
So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...
FPGA Assemblers and Time Machines
Flashback to 1986. A young man has a crazy idea - he wants to make a CPU all by himself. He is reading early Xilinx manuals cover to cover as if they were novels. Yes, you are quick - this is indeed a (mostly) true story about me and my dream, suddenly made possible by this new FPGA technology.
Sadly more than 20 years went by before my first CPU ran in a Xilinx FPGA. Why did it take so long? Every few years I set up the tools and every time I walked away, scared silly. As the years...
Grandiose Delusions
Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools. In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL. For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.
Many design languages have relied on that first big...
State Machine ‘v’ Micro in a FPGA
Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.
We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...
Are you kidding me?
If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost. The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows). A quote from the blog.
... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...
C/C++/SystemC, are you kidding...
Cutting a Path Forward
IntroductionAs a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.
My day job is as a professional software developer: Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.
By night, however, I've been working on my...
Choosing an Implementation Approach
What one man can do, another can do!--The Edge (1997) Choose the hill you want to die on.--Common saying attributed to the United States Marine Corps Planning out an FPGA ImplementationIn my first article, I gave a high-level view of the project that brings me into the world of FPGA development. At the end, I tried to break down the areas of development that would be involved, and some of the knowledge and expertise I would probably have to gain in order to make it a...
Grandiose Delusions
Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools. In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL. For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.
Many design languages have relied on that first big...