PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


VGA Output in 7 Slices. Really.

Victor Yurkovsky September 25, 20122 comments

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...


How to start in FPGA development? - Simulation software tools

Nuria Orduna September 19, 20128 comments
Introduction

This post is related to the first post How to start in FPGA development? - Some tips which aimed to show other options to work on the simulation of your project. In this first approach will be explained some advantages and disadvantages of using Xilinx ISE (+ModelSim) or using ModelSim, Precision and Xilinx ISE. And finally my opinion of which are the ones I...


How to start in FPGA development? - Some tips

Nuria Orduna August 30, 20123 comments
Introduction

The aim of this tutorial is to show some useful tips for people like me that one day started from zero to work with FPGA's. Why FPGA's? Because they are easy to use and they are not too expensive, and they are usually used in lab courses to let students "play" with them.

1: How to choose the right FPGA?

As you may know there are a lot of different FPGA's, brands and models. How to choose the right one? It's very difficult to say that before knowing which will be the...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012
Introduction

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....


An Editor for HDLs

Dave Vandenbout July 17, 201211 comments

Unless you're still living in the '90s and using schematics, your FPGA designs are entered into text files as VHDL or Verilog source. Which, of course, implies you're using some form of text editor. Now, right after brace placement in C, the choice of an editor is the topic most likely to incite a nerd civil war (it's a bike-shed issue). I won't attempt to influence your choice because it really makes no difference to me. But if you are using the same editor I do, then maybe I can help you...


My VHDL <= monpjc; Journey

Paul J Clarke March 18, 20121 comment

I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.

It started a long time ago when I was working for a...


Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015
Introduction

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...


Tools of the Trade: reading PDFs (and keeping bookmarks)

Victor Yurkovsky July 7, 20155 comments

In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.

Some days I sit down to work and wonder how anything ever gets done. A simple example.  When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format.  There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it.  While...


PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


MyHDL Interface Example

Christopher Felton January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

One Clock Cycle Polynomial Math

Mike November 20, 201514 comments

Error correction codes and cryptographic computations are most easily performed working with $GF(2^n)$  polynomials.  By using very special values of $n$ we can build circuits which multiply and square in one clock cycle on an FPGA. These circuits come about by flipping back and forth between a standard polynomial basis and a normal basis representation of elements in $GF(2^n)$.

A normal basis is yet another form of polynomial but instead of adding powers of $\beta$ we add...


Polynomial Inverse

Mike November 23, 20152 comments

One of the important steps of computing point addition over elliptic curves is a division of two polynomials.  When working in $GF(2^n)$ we don't have large enough powers to actually do a division, so we compute the inverse of the denominator and then multiply.  This is usually done using Euclid's method, but if squaring and multiplying are fast we can take advantage of these operations and compute the multiplicative inverse in just a few steps.

The first time I ran across this...


MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


My VHDL <= monpjc; Journey

Paul J Clarke March 18, 20121 comment

I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.

It started a long time ago when I was working for a...