MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


MyHDL Resources and Projects

Christopher Felton December 9, 20122 comments

Last updated 07-Nov-2017

MyHDL Resources

If you want to dive into MyHDL (digital hardware description in Python) there are many resources available.  Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.

The MyHDL manual is a great (probably the best) place to get started.

The manual is an in-depth introduction to MyHDL.  The concepts are well explained and there are examples to test while working through the...


MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)

Christopher Felton September 13, 201210 comments
Introduction

To demonstrate the echo on an FPGA board an interface to an audio ADC/DAC chip will be used. The following will explain the connection to the audio codec and the HDL module used to interface.

Audio Codec Interface

I have two boards with TI AIC23b audio codecs. The AIC23 has a configuration interface (ability to program the registers) and a streaming audio interface. The SPI mode will be used to configure the codec and the I2S interface is used to send and...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012
Introduction

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....


An Editor for HDLs

Dave Vandenbout July 17, 201211 comments

Unless you're still living in the '90s and using schematics, your FPGA designs are entered into text files as VHDL or Verilog source. Which, of course, implies you're using some form of text editor. Now, right after brace placement in C, the choice of an editor is the topic most likely to incite a nerd civil war (it's a bike-shed issue). I won't attempt to influence your choice because it really makes no difference to me. But if you are using the same editor I do, then maybe I can help you...


Are you kidding me?

Christopher Felton July 1, 2012

If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost.  The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows).  A quote from the blog.

... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...

C/C++/SystemC, are you kidding...


Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...


My VHDL <= monpjc; Journey

Paul J Clarke March 18, 20121 comment

I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.

It started a long time ago when I was working for a...


MyHDL FPGA Tutorial I (LED Strobe)

Christopher Felton January 31, 20126 comments

Last updated 05-Nov-2015

Introduction

From many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources.  Even the devices that one can get for sub \$10 are relatively large.  Because of the size of these FPGAs they are implemented using an HDL.  To manually configure each circuit would be a long and tedious task.  It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...


Verilog vs VHDL

Muhammad Yasir June 13, 2011

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...


MyHDL Resources and Projects

Christopher Felton December 9, 20122 comments

Last updated 07-Nov-2017

MyHDL Resources

If you want to dive into MyHDL (digital hardware description in Python) there are many resources available.  Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.

The MyHDL manual is a great (probably the best) place to get started.

The manual is an in-depth introduction to MyHDL.  The concepts are well explained and there are examples to test while working through the...


An absolute position encoder VHDL core

Fabien Le Mentec November 11, 2015
Introduction

Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:

The following components are involved:

  • the motor itself (DC, stepper ...),
  • the controller, in charge of computing position according to the whole system state,
  • the driver board in charge of generating signals and power for the motor,
  • the position encoder, the subject of this post.

Most of the time, there is a difference between the position the system...


Introducing the VPCIe framework

Fabien Le Mentec August 31, 20133 comments
Introduction

My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...


MyHDL Interface Example

Christopher Felton January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

MyHDL synthesis: from browser to FPGA in five seconds

Martin Strubel May 22, 2020

When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.

So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...


MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


Are you kidding me?

Christopher Felton July 1, 2012

If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost.  The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows).  A quote from the blog.

... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...

C/C++/SystemC, are you kidding...


Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...


Point of View

Christopher Felton August 28, 20146 comments

I was caught of guard when someone commented:

"when a FIR filter is full of multiple loops and complex code, something is wrong"

The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL

(different FIR description simulation results) 

Personally, (and...


MyHDL Presentation Examples

Christopher Felton August 26, 2014

The last two years I presented at EELive.  The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper].  The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL.  I also presented at a regional Python conferene: pyohio.  At the Python conference I presented...