VGA Output in 7 Slices. Really.

Victor Yurkovsky September 25, 20122 comments

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...


Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke June 26, 20121 comment

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...


USB-FPGA : Introduction

Christopher Felton January 12, 20111 comment

This blog is an introduction to a series of blogs I hope to write.  The blogs will cover the design and experiences I had on a project that spanned the last 6 years.  The project was the development of an USB FPGA board and the supporting gateware, firmware, and software.  The project has had different levels of activity over the years, ranging from none to some, but it has been an ongoing project, albeit, during sleepless nights.  Lately, I have ported the HDL (gateware)...


A Bit Bucket had Holes

Christopher Felton July 28, 20101 comment

Couple months ago I wrote a quick little blog about a company called Tabula.  Tabula has a virtual 3D approach to achieving higher logic density in an FPGA.  See the previous blog for more information.

Along similar lines was another company called TierLogic which actually had multiple physical layers.  I was impressed with the Tabula approach and claims.  Along the same lines the TierLogic technology looked promising as well.  But, EE Times has reported that...


The Spartans

Christopher Felton February 20, 20104 comments

The latest release of the Xilinx Spartan family is the Spartan6 line of FPGAs. It has been awhile since the last major Spartan released, the Spartan3, but this last year Xilinx released the Spartan6. The Xilinx Spartan family is the low cost FPGAs compared to the higher cost and high performance Virtex family. The Spartan family is derived from the Virtex architecture with some changes to reduce the cost. The Spartan3 FPGAs were derived from the Virtex-II architecture. Since the Spartan3...


PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


MyHDL Interface Example

Christopher Felton January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke June 26, 20121 comment

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...


[Comments] C HLS Benefits

Christopher Felton April 11, 20142 comments

Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL.  For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).

Language comparisons...


A Bit Bucket had Holes

Christopher Felton July 28, 20101 comment

Couple months ago I wrote a quick little blog about a company called Tabula.  Tabula has a virtual 3D approach to achieving higher logic density in an FPGA.  See the previous blog for more information.

Along similar lines was another company called TierLogic which actually had multiple physical layers.  I was impressed with the Tabula approach and claims.  Along the same lines the TierLogic technology looked promising as well.  But, EE Times has reported that...