Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
Do you have a Twitter and/or Linkedin account?
If you do, please consider paying close attention for the next few days to the EmbeddedRelated Twitter account and to my personal Linkedin account (feel free to connect). This is where I will be posting lots of updates about how the EmbeddedRelated.tv live streaming experience is going at Embedded World.
The most successful this live broadcasting experience will be, the better the chances that I will be able to do it...
Launch of EmbeddedRelated.tv
Stephane Boucher launches EmbeddedRelated.tv to host live broadcasts from Embedded World, starting next week. The site will show a constantly evolving schedule, a Live! tab to find ongoing streams, and ad-hoc demos added from the show floor. Expect schedule conflicts and small hiccups, and plan to refresh the page and join the forum thread for real-time updates and feedback.
Live Streaming from Embedded World!
Stephane Boucher will bring Embedded World to engineers who cannot attend, streaming high-quality HD video from the show floor. He plans to use a professional camera and a device that bonds three internet links to keep the stream stable, and he is coordinating live sessions with vendors and select talks. Read on to learn how to vote for the presentations you want streamed.
What to See at Embedded World 2019
Skip the overwhelm at Embedded World 2019, Stephane Boucher lays out a practical preview of what to see and how to prioritize your time. The post helps embedded engineers focus on demos, vendor booths, and sessions that matter without getting lost on the show floor. Read it to plan a short, efficient visit that maximizes technical takeaways and networking opportunities.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.
I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Jason Sachs demystifies linear feedback shift registers with a practical, bitwise view and the algebra that explains why they work. Readable examples compare Fibonacci and Galois implementations, show a simple software implementation, and reveal the correspondence between N-bit Galois LFSRs and GF(2^N) so you can pick taps and reason about maximal-length pseudorandom sequences.
Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes
Stephane Boucher tried live-streaming multiple talks from Embedded World 2019 and turned a chaotic experiment into a useful set of lessons for embedded engineers. Between broken tripods, flaky venue WiFi, tricky German SIM purchases, and audio nightmares, he learned practical fixes for reliable streams and better video quality. Read this if you want candid, tactical advice on streaming hardware, connectivity, and on-site troubleshooting.
VHDL tutorial - combining clocked and sequential logic
Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.
Oscilloscope Dreams
Jason Sachs walks through practical oscilloscope buying criteria for embedded engineers, focusing on bandwidth, channel count, hi-res acquisition, and probing. He explains why mixed-signal scopes and hi-res mode matter, when a 100 MHz scope is sufficient and when to keep a higher-bandwidth instrument, and how probe grounding and waveform export can ruin measurements. Real-world brand notes and try-before-you-buy advice round out the guidance.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
The DSP Online Conference - Right Around the Corner!
Three months after a forum post, Stephane Boucher and Jacob Beningo pulled together the DSP Online Conference, a two-day virtual event featuring 14 talks from leading DSP experts. Most sessions are 30 to 60 minutes with a 30-minute Zoom Q&A, while extended deep dives from speakers like fred harris are included. Registered attendees get one-year on-demand access, and free or reduced passes are available.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
A New Related Site!
The post announces the launch of MLRelated, a new Related site dedicated to machine learning and deep learning. It positions MLRelated as complementary to existing Related sites by highlighting cross-cutting interests: TinyML for embedded developers, machine/deep learning applications in signal processing, and FPGA-based AI/ML implementations. The new site debuts with a modest amount of content and is expected to expand rapidly through contributions from the Related community in the form of blogs, forum threads, and webinars. The author invites readers to report navigation errors, share feedback, and propose ideas to help steer MLRelated into a practical, community-driven resource for researchers and practitioners in ML and adjacent domains.
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.
Oscilloscope Dreams
Jason Sachs walks through practical oscilloscope buying criteria for embedded engineers, focusing on bandwidth, channel count, hi-res acquisition, and probing. He explains why mixed-signal scopes and hi-res mode matter, when a 100 MHz scope is sufficient and when to keep a higher-bandwidth instrument, and how probe grounding and waveform export can ruin measurements. Real-world brand notes and try-before-you-buy advice round out the guidance.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Elliptic Curve Cryptography - Basic Math
An introduction to the math of elliptic curves for cryptography. Covers the basic equations of points on an elliptic curve and the concept of point addition as well as multiplication.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Launch of Youtube Channel: My First Videos - Embedded World 2017
Stephane Boucher turned his Embedded World 2017 trip into a debut YouTube series of short booth highlight videos. He walks through the steep learning curve of trade-show filming, the specific gear he bought and rented to cope with low light and noise, and the practical mistakes he plans to fix. The post lists filmed vendors and asks readers for feedback to improve future episodes.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
The New Forum is LIVE!
After months of hard word, I am very excited to introduce to you the new forum interface.
Here are the key features:
1- Easily add images to a post by drag & dropping the images in the editor
2- Easily attach files to a post by drag & dropping the files in the editor
3- Add latex equations to a post and they will be rendered with Mathjax (tutorial)
4- Add a code snippet and surround the code with
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Two jobs
Stephane Boucher explains why EmbeddedRelated went quiet for a few months after a volunteer project demanded more of his time. He and his wife organized a clown-gymnastics show with 15 kids, sold more than 700 of 800 tickets, and raised $2,700 for the Tree of Hope. Now the shows are done and he plans to resume regular posting with new site features.
FPGA Bloggers Needed - New Reward System
You can earn up to $500 for a single FPGA blog post on FPGARelated. Stephane Boucher announces a new pageview-based reward system that pays $25 for every 250 unique pageviews, capped at $500 when a post reaches 5,000 views. If you write about Verilog, VHDL, or FPGA design and want to share expertise while getting paid, fill the short application form to apply.
