Developing FPGA-DSP IP with Python
This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.
Developing FPGA-DSP IP with Python / MyHDLUsing Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...
VHDL tutorial
When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.
I have continued to incorporate these powerful blocks into many of my latest designs. My current favorite part line is the Xilinx CoolRunner series (XC2Cxxx). In this...
Point of View
I was caught of guard when someone commented:
"when a FIR filter is full of multiple loops and complex code, something is wrong"The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL:
(different FIR description simulation results)
Personally, (and...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
My VHDL <= monpjc; Journey
I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.
It started a long time ago when I was working for a...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
