Steve Maslen Blog on FPGARelated.com

Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

Steve Maslen — Tue, 18 Jun 2019 13:49:50 +0000

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.

Some applications demand zero-latency or zero unwanted latency signal processing. Negative...

Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

Steve Maslen — Thu, 22 Nov 2018 14:56:32 +0000

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs....

Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

Steve Maslen — Mon, 09 Jul 2018 14:26:22 +0000

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB)...

Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

Steve Maslen — Wed, 21 Mar 2018 18:17:29 +0000

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the...

Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

Steve Maslen — Fri, 05 Jan 2018 11:55:33 +0000

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.

Comparisons will be made between implementations on Intel Cyclone V and

Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

Steve Maslen — Sun, 03 Dec 2017 17:26:13 +0000

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website

Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

Steve Maslen — Tue, 14 Nov 2017 17:50:32 +0000

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website

Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Steve Maslen — Tue, 10 Oct 2017 13:24:18 +0000

Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the

Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

Steve Maslen — Sat, 09 Sep 2017 13:59:35 +0000

Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to...

Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Steve Maslen — Thu, 24 Aug 2017 17:25:07 +0000

Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Steve Maslen — Tue, 22 Aug 2017 16:24:21 +0000

Introduction to the topic

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and...