https://www.fpgarelated.com/blogs-1/nf/Sriyash_Caculo.php https://www.fpgarelated.com/blogs-1/nf/Sriyash_Caculo.php https://d23s79tivgl8me.cloudfront.net/user/profilepictures/128727.jpg en-US Fri, 10 Apr 2026 13:01:38 +0000 1775826098 https://www.fpgarelated.com/showarticle/1176/project-introduction-digital-filter-blocks-in-myhdl-and-their-integration-in-pyfda Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus  pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing...]]> Fri, 25 May 2018 13:39:44 +0000 Sriyash Caculo