Gene Breniman Blog on FPGARelated.com https://www.fpgarelated.com/blogs-1/nf/Gene_Breniman.php Gene Breniman Blog on FPGARelated.com https://www.fpgarelated.com/blogs-1/nf/Gene_Breniman.php https://d23s79tivgl8me.cloudfront.net/user/profilepictures/70472.jpg en-US Fri, 10 Apr 2026 13:26:18 +0000 1775827578 VHDL tutorial - A practical example - part 3 - VHDL testbench https://www.fpgarelated.com/showarticle/266/vhdl-tutorial-a-practical-example-part-3-vhdl-testbench In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part.  In part 2, we described the VHDL logic of the CPLD for this design.  In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what...]]> Sun, 26 Jun 2011 00:20:25 +0000 Gene Breniman VHDL tutorial - A practical example - part 2 - VHDL coding https://www.fpgarelated.com/showarticle/264/vhdl-tutorial-a-practical-example-part-2-vhdl-coding

In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part.  In part 2, we will describe the VHDL logic of the CPLD for this design.

With any design, the first step to gather the requirements for the job at hand.  From part 1 of this article, I have copied two sections that address...]]> Fri, 27 May 2011 20:12:13 +0000 Gene Breniman VHDL tutorial - A practical example - part 1 - Hardware https://www.fpgarelated.com/showarticle/262/vhdl-tutorial-a-practical-example-part-1-hardware

In previous posts I described some simple VHDL examples.  This time let's try something a little more complex. This is part one of a multiple part article.  This is intended to be a detailed description of one of several initial designs that I developed for a client.  This design never made it into a product, but a similar design was used and is currently being...]]> Wed, 18 May 2011 15:44:37 +0000 Gene Breniman VHDL tutorial - Creating a hierarchical design https://www.fpgarelated.com/showarticle/239/vhdl-tutorial-creating-a-hierarchical-design

In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and ' Thu, 22 May 2008 17:28:01 +0000 Gene Breniman VHDL tutorial - combining clocked and sequential logic https://www.fpgarelated.com/showarticle/228/vhdl-tutorial-combining-clocked-and-sequential-logic

In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a...]]> Mon, 03 Mar 2008 18:33:22 +0000 Gene Breniman VHDL tutorial - part 2 - Testbench https://www.fpgarelated.com/showarticle/216/vhdl-tutorial-part-2-testbench

In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE environment makes it pretty easy to start the testing process. To start the process, select "New Source" from the menu items under "Project". This launches the "New Source Wizard". From...]]> Tue, 30 Oct 2007 19:14:14 +0000 Gene Breniman VHDL tutorial https://www.fpgarelated.com/showarticle/208/vhdl-tutorial When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.

I have continued to incorporate these powerful blocks into many of...]]> Thu, 04 Oct 2007 23:44:26 +0000 Gene Breniman