Martin Strubel Blog on FPGARelated.com

MyHDL synthesis: from browser to FPGA in five seconds

Martin Strubel — Fri, 22 May 2020 10:31:59 +0000

When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.

So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then...

Using GHDL for interactive simulation under Linux

Martin Strubel — Mon, 24 Oct 2011 16:12:36 +0000

The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I hope this short overview will change your mind and even whet your appetite for more. Because, using some extensions, you can do some quite funky...