Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke — Tue, 26 Jun 2012 18:32:03 +0000

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGA

Designing a FPGA Micro Pt1 - Start The Clock

Paul J Clarke — Tue, 22 May 2012 18:42:42 +0000

Last time I talked about state machines and micro’s inside FPGAs and why you may want to consider having a micro. So lets say you have decided you want or need a micro in your FPGA design. Where will you start? Well there are lots to pick from but one option is to design your own. So with that in mind I decided to set myself the challenge of doing just that.

We first look...

My VHDL <= monpjc; Journey

Paul J Clarke — Sun, 18 Mar 2012 20:54:32 +0000

I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me,...

Paul J Clarke Blog on FPGARelated.com

Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Designing a FPGA Micro Pt1 - Start The Clock

My VHDL <= monpjc; Journey