The Art of Verification with SystemVerilog Assertions
The Art of Verification with SystemVerilog Assertions (SVA) covers all aspects of SVA with numerous, detailed examples. The book demonstrates how SVA can be harnessed to implement effective, assertion-based verification.
It teaches the SVA language by explaining its usage in the context of practical verification issues. SVA syntax and features are explained in simple and easy-to-understand language. The usage of each construct is illustrated with both simple examples and examples drawn from common verification problems. SVA is used to develop an effective, assertion-based verification strategy for an OCP cache.
Why Read This Book
You should read this book if you want a hands-on, example-led introduction to writing effective SystemVerilog Assertions and using them as the backbone of an assertion-based verification strategy. It teaches SVA constructs in the context of real verification problems (including a worked OCP cache case study), so you’ll quickly learn patterns you can apply to your own testbenches and checks.
Who Will Benefit
Verification engineers and RTL designers with some HDL experience who need to add robust assertion-based checks and temporal properties to simulation and formal flows.
Level: Intermediate — Prerequisites: Familiarity with Verilog or SystemVerilog basics, digital logic design, and general verification concepts such as testbenches and functional coverage.
Key Takeaways
- Write and debug SVA sequences, properties, and temporal expressions to capture protocol and functional intent.
- Apply assertions for protocol checking, illegal-state detection, and runtime monitoring in simulation.
- Integrate assertion-based checks into a verification strategy and use them with coverage to improve verification closure.
- Use assertions as a bridge to formal/automatic checking techniques and feed practical examples to formal engines.
- Design and instrument assertions in real-world contexts using the OCP cache case study as a blueprint.
- Diagnose common verification pitfalls and build reusable assertion templates for testbenches.
Topics Covered
- Introduction to Assertion-Based Verification and SVA
- SVA Fundamentals: Sequences, Properties, and Operators
- Temporal Expressions and Timing Control
- Binding Assertions to Design Instances and Interfaces
- Practical Patterns: Protocol Checks and Illegal-State Assertions
- Coverage and Assertion-Driven Coverage Metrics
- Assertion-Based Verification Methodology
- Integration with Simulation and Formal Tools
- Worked Example: Building an Assertion Suite for an OCP Cache
- Debugging, Reporting, and Best Practices
- Advanced SVA Features and Practical Tips
- Appendices: SVA Syntax Reference and Useful Idioms
Languages, Platforms & Tools
How It Compares
More narrowly focused on SVA and packed with practical examples than broader texts like "SystemVerilog for Verification" (Chris Spear); complements general assertion books such as "Assertion-Based Verification" by Foster et al. by emphasizing applied patterns and a concrete case study.
