The Designer's Guide to VHDL (Systems on Silicon)
The Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from system level down to gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
The book is organized so that it can either be read cover to cover for a comprehensive tutorial or be kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. In addition, each chapter is followed by a set of rated exercises.
Why Read This Book
You should read this book if you want a deep, authoritative grounding in VHDL: it teaches the language from fundamentals through practical modeling styles and synthesizable RTL, and it doubles as a reliable desk reference. You will gain a clear methodology for writing readable, maintainable VHDL and for moving models from simulation to FPGA implementation.
Who Will Benefit
Engineers and students designing digital systems or FPGA RTL who need a thorough VHDL reference and practical modeling methodology.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with combinational/sequential circuits; minimal programming experience is helpful but not required.
Key Takeaways
- Model combinational and sequential circuits using VHDL's behavioral, dataflow, and structural styles
- Apply the IEEE VHDL language constructs, types, and standard packages correctly
- Write synthesizable RTL and recognize language constructs that affect synthesis and implementation
- Build effective testbenches and use simulation semantics and timing to validate designs
- Organize designs with packages, configurations, and libraries for reusable, maintainable code
- Analyze and map VHDL abstractions to gate-level/FPGA implementation considerations (timing, resources)
Topics Covered
- Introduction to VHDL and modeling methodology
- Lexical conventions, identifiers, and declarations
- Scalar and composite data types; arrays and records
- Operators, expressions, and type conversion
- Concurrent statements and signal assignment
- Sequential statements and process modeling
- Subprograms, procedures, and functions
- Packages, libraries, and design units
- Structural, dataflow, and behavioral modeling styles
- Simulation semantics, delta cycles, and time handling
- Testbench design and verification techniques
- Synthesis considerations and synthesizable subset
- Configurations, binding, and hierarchical design
- Low-level and gate-level modeling; practical examples
- Appendices: language reference and standard packages
Languages, Platforms & Tools
How It Compares
More authoritative and standards-focused than Perry's VHDL tutorials — Ashenden is deeper as a language reference and modeling methodology guide, while some alternatives (e.g., Douglas Perry) are more example-driven and shorter.
