VHDL Answers to Frequently Asked Questions
VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. TItis book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages of common utilities that are useful in the generation of debug code and testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.
Why Read This Book
You should read this book if you want concise, practical answers to everyday VHDL questions that crop up during design, simulation, and synthesis. It collects real-world advice and gotchas from the VHDL community so you can avoid common mistakes, write synthesis-friendly code, and build more robust testbenches faster.
Who Will Benefit
Intermediate VHDL designers and FPGA engineers who already know the basics and want to eliminate common synthesis/simulation pitfalls and improve code quality and verification practices.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with VHDL syntax and semantics (processes, signals, types) plus some exposure to simulation and synthesis tools.
Key Takeaways
- Identify and avoid common VHDL language pitfalls that cause simulation/synthesis mismatches.
- Write synthesis-friendly VHDL coding patterns that are portable across tools.
- Create effective, simulation-efficient testbenches and verification strategies.
- Apply practical guidelines for data types, signal assignment, and concurrency to improve reliability.
- Diagnose typical tool-specific synthesis issues and workarounds for FPGA flows.
- Adopt coding styles that improve readability, maintainability, and reuse in hardware projects.
Topics Covered
- Preface and how this FAQ was compiled
- VHDL language pitfalls and misunderstood constructs
- Data types, operators and type conversion issues
- Processes, concurrency and signal vs variable semantics
- Coding styles for synthesis and portability
- Common synthesis problems and tool-specific notes
- Testbench techniques and simulation efficiency
- Clocking, resets and timing-related design advice
- Verification practices and debugging strategies
- Guidelines for FPGA implementations (practical tips)
- Frequently asked Q&A (organized by topic)
- Appendices: VHDL-93 notes, references, and further reading
Languages, Platforms & Tools
How It Compares
More pragmatic and community-driven than Peter Ashenden's Designer's Guide to VHDL (which is a formal reference); complements Cohen's own VHDL Coding Styles and Methodologies by focusing on the frequently encountered questions and tool-era gotchas.
