Vhdl for Logic Synthesis
VHDL for Logic Synthesis Second Edition Andrew Rushton TransEDA Limited, Southampton, UK Very high-speed integrated circuit Hardware Description Language (VHDL) is the worldwide standard for computer-aided electronic system design. Logic synthesis automates gate-level design, allowing the designer to concentrate on a rgister-transfer level implementation. VHDL for Logic Synthesis provides comprehensive coverage of the language and its role in the generation of hardware. This enhanced second edition takes a broader view of the use of synthesis and its place in the design cycle. Features include:
* Explanation of each aspect of the language in hardware terms and demonstration of the mapping from VHDL to hardware
* Updated examples using the standard packages numeric_std and std_logic_1164 plus more illustrative models offering further source references for designers
* Additional chapter on std_logic_arith to aid designers still working with this popular package
* New focus on libraries and library management covering the contents of the standard library, how to use library work and recommendations on code management
* Extra section detailing how to use assertions to report diagnostics, allowing the reader to print signal and variable values to the screen
Senior undergraduate and postgraduate students of microelectronics and digital hardware engineers new to language-based design methods will appreciate Rushton's informative introduction to VHDL and its use in logic synthesis.
Why Read This Book
You will learn how VHDL constructs translate to real hardware and how to write RTL that synthesizes efficiently and predictably. The book gives practical, synthesis-driven coding rules, worked examples and mapping guidance that help you avoid non‑synthesizable pitfalls and get clean gate-level results.
Who Will Benefit
FPGA and ASIC designers or verification engineers with some HDL experience who need practical guidance on writing synthesizable VHDL and mapping RTL to hardware.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with HDL concepts; some prior exposure to VHDL syntax or other hardware description languages will help.
Key Takeaways
- Write synthesizable VHDL that maps cleanly to registers, LUTs and gates
- Design and implement RTL finite-state machines and synchronous logic using synthesis-friendly styles
- Use std_logic_1164 and numeric_std correctly for robust, portable arithmetic and bit-level operations
- Avoid common non-synthesizable constructs and understand synthesis tool limitations
- Structure hierarchical designs and modules in a way that eases synthesis and optimization
- Apply practical synthesis guidelines to improve area, timing predictability, and tool flow compatibility
Topics Covered
- Introduction: VHDL and the role of logic synthesis
- The VHDL language: data types, operators and concurrency
- Standard packages: std_logic_1164 and numeric_std
- Combinational modeling and synthesis mapping
- Sequential elements: registers, clocks and reset conventions
- Finite-State Machines: modeling and synthesis-friendly styles
- Arithmetic, vectors and arrays: synthesisable implementations
- Memories, ROMs and RAMs: synthesis and inference
- Structuring designs: hierarchy, components and generics
- Synthesis pragmas, attributes and tool hints
- Timing, clocks and clock-domain issues
- Testbench vs. synthesis: what to simulate and what synthesizers accept
- Practical examples and case studies
- Guidelines for optimizing synthesis results and debugging
Languages, Platforms & Tools
How It Compares
More synthesis-focused and practical than Peter Ashenden's The Designer's Guide to VHDL (which is a deeper language reference); complements VHDL tutorials like Navabi's VHDL for Engineers by emphasizing synthesis mapping and coding rules.
