Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification
This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.
Why Read This Book
You should read this book if you want a focused, engineering-oriented guide to writing synthesizable Verilog RTL and building robust testbenches — it bridges language syntax with practical synthesis and verification practice. You will get worked examples and concrete coding guidelines that help avoid common synthesis/simulation mismatches and improve verification productivity.
Who Will Benefit
Intermediate digital/FPGA/ASIC engineers or senior students who know basic digital design and want to produce synthesizable Verilog and dependable verification environments.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with introductory Verilog (modules, wires, regs); some exposure to simulation tools is helpful.
Key Takeaways
- Write synthesizable Verilog-2001 RTL using industry-appropriate coding styles.
- Apply synthesis guidelines to avoid common pitfalls and simulation vs. synthesis mismatches.
- Design and implement finite-state machines and common datapath/control structures in RTL.
- Develop structured testbenches and use the OVI verification library for automated verification.
- Use synthesis and simulation tools in a design flow and interpret synthesis reports.
- Create test vectors and think about fault coverage and basic test generation strategies.
Topics Covered
- Introduction: Digital Design Flow and Verilog Overview
- Verilog Language Essentials (data types, operators, expressions)
- Modeling Styles: Behavioral, Dataflow and Structural
- Timing, Concurrency and Simulation Semantics
- RTL Coding Techniques and Synthesizable Constructs
- Finite-State Machine Design and Encoding
- Combinational and Sequential Logic Synthesis
- Synthesis Guidelines and Common Pitfalls
- Testbench Development and Verification Principles
- OVI (Open Verification Library) and Verification Libraries
- Test Generation, Fault Coverage and Scan/DFT Considerations
- Tool Flows: Simulation, Synthesis and Implementation
- Worked Examples and Case Studies
Languages, Platforms & Tools
How It Compares
More synthesis- and verification-oriented than Palnitkar's Verilog HDL (which is a gentler language tutorial); it predates and lacks SystemVerilog-era verification features covered in newer books such as Sutherland's SystemVerilog-focused texts.
