Essential Vhdl: Rtl Synthesis Done Right
This book: - demonstrates practical synthesis techniques - contains several real-world design examples - illustrates synthesis results using gate-level circuits - focuses on the std_logic type and its related functions - discusses, in detail, state machines, partitioning and hardware creation
Why Read This Book
You should read this book if you want a hands-on, synthesis-centered guide to writing synthesizable VHDL: it walks through coding techniques, realistic examples and shows gate-level synthesis results so you can see how VHDL maps to hardware. It emphasizes practical rules and patterns (especially around std_logic and state machines) that help you produce RTL that synthesizes predictably.
Who Will Benefit
Intermediate digital/FPGA engineers or designers who already know basic VHDL and want to learn synthesis-friendly coding styles, FSM design, and how high-level VHDL constructs translate to gates.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with VHDL syntax (entities, architectures, signals, processes).
Key Takeaways
- Write synthesizable VHDL that maps predictably to gate-level hardware
- Design and implement robust finite state machines using synthesis-friendly styles
- Optimize RTL structure through partitioning and hierarchical design to influence area and timing
- Apply correct std_logic and std_logic_vector usage and related functions for reliable synthesis
- Interpret synthesis reports and gate-level results to validate and refine HDL code
Topics Covered
- Introduction: VHDL and Synthesis
- VHDL Data Types with focus on std_logic
- Combinational Logic Coding Styles
- Sequential Logic and Registers
- Finite State Machines: Design and Coding
- Arithmetic, Buses and Signal Manipulation
- Partitioning, Hierarchy and Hardware Creation
- Synthesis Results and Gate-Level Analysis
- Practical Design Examples and Case Studies
- Timing Considerations and Basic Optimization
- Design-for-Test and Implementation Notes
- Appendices: Useful VHDL Idioms and Synthesis Guidelines
Languages, Platforms & Tools
How It Compares
More synthesis-focused and example-driven than Peter Ashenden's The Designer's Guide to VHDL (which is a broader language reference); closer in spirit to pragmatic VHDL how‑tos like Pedroni's synthesis-oriented texts but with a stronger emphasis on showing gate-level mapping.
