The Verilog® Hardware Description Language
XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
Why Read This Book
You should read this book if you want a thorough, standards-aware grounding in Verilog HDL: it walks from tutorial material to synthesizable RTL idioms, testbench practice, and synthesis rules. It’s useful both as a learning text and as a reference when you need authoritative explanations of Verilog semantics and synthesizable constructs.
Who Will Benefit
Engineers and students who design RTL for FPGAs or ASICs and need a standards-aligned reference on Verilog coding, simulation, and synthesis.
Level: Intermediate — Prerequisites: Basic digital logic (combinational/sequential circuits), basic programming experience (procedural thinking), and familiarity with binary/hex notation.
Key Takeaways
- Write synthesizable Verilog RTL using accepted coding styles and synthesis rules
- Model combinational and sequential logic, including finite state machines, with both behavioral and structural approaches
- Build effective testbenches and use Verilog simulation constructs and system tasks for verification
- Understand differences between blocking and non-blocking assignment and when to use each
- Apply Verilog constructs that map cleanly to FPGA/ASIC implementation tools
- Interpret and use Verilog data types, operators, and procedural rules correctly to avoid common pitfalls
Topics Covered
- Preface and Tutorial Introduction
- Lexical Elements, Modules, and Ports
- Structural Descriptions and Gate-Level Modeling
- Behavioral Modeling of Combinational Circuits
- Procedural Models and Procedural Blocks
- Clocked Sequential Circuits and FSM Modeling
- Rules for Synthesizing Combinational and Sequential Logic
- Blocking vs. Non-blocking Assignments and Timing Semantics
- Testbenches, Simulation, and System Tasks
- Advanced Language Features and Verilog-2001 Additions
- Synthesis Guidelines and Coding Style Recommendations
- Appendices: Reference Tables and Language Summary
Languages, Platforms & Tools
How It Compares
Similar ground to Samir Palnitkar's 'Verilog HDL' but more authoritative/standards-focused (and closer to the LRM); Palnitkar is often seen as a more tutorial, beginner-friendly alternative.
