VHDL for Engineers
Suitable for use in a one- or two-semester course for computer and electrical engineering majors.
VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
Why Read This Book
You should read this if you want a clear, classroom-tested introduction to writing synthesizable VHDL for real PLD/FPGA projects; it walks you from language basics to practical simulation, testbenches, and implementation issues. The book balances language syntax, design examples, and synthesis considerations so you can move quickly from learning constructs to building deployable hardware.
Who Will Benefit
Undergraduate EE/CE students or engineers new to HDLs who need a practical, example-driven introduction to VHDL for FPGA/CPLD design and implementation.
Level: Beginner — Prerequisites: Basic digital logic (combinational/sequential circuits) and a minimal programming background (pseudocode or basic procedural programming).
Key Takeaways
- Write synthesizable VHDL descriptions for combinational and sequential circuits.
- Create and run VHDL testbenches to simulate and verify designs.
- Design finite-state machines and implement them in VHDL using good RTL practice.
- Modularize designs using entities, architectures, packages, and generics.
- Understand synthesis constraints and map VHDL constructs to CPLD/FPGA resources.
- Use common simulation and implementation tools to go from VHDL code to a programmed device.
Topics Covered
- Introduction: VHDL and the PLD/FPGA Design Flow
- VHDL Basic Concepts and Lexical Elements
- Data Types, Objects, and Operators
- Concurrent Statements and Structural Modeling
- Sequential Statements and Processes
- Modeling Combinational and Sequential Circuits
- Designing Finite State Machines in VHDL
- Testbenches, Simulation, and Verification
- Synthesis Guidelines and Implementation on CPLDs/FPGAs
- Arithmetic, Signed/Unsigned, and Numeric Packages
- Libraries, Packages, and Generic Design
- Design Examples and Laboratory Projects
- Appendices: Reserved Words, Useful Tables, and Tool Notes
Languages, Platforms & Tools
How It Compares
Covers similar classroom material to Brown & Vranesic's Fundamentals texts but is more VHDL-focused and example-driven; less deep in language semantics and advanced topics than Ashenden's The Designer's Guide to VHDL.
