The Boundary ― Scan Handbook
In February of 1990, the balloting process for the IEEE proposed standard P1149.1 was completed creating IEEE Std 1149.1-1990. Later that summer, in record time, the standard won ratification as an ANSI standard as well. This completed over six years of intensive cooperative effort by a diverse group of people who share a vision on solving some of the severe testing problems that exist now and are steadily getting worse. Early in this process, someone asked me if 1 thought that the P1l49.l effort would ever bear fruit. 1 responded somewhat glibly that "it was anyone's guess". Well, it wasn't anyone's guess, but rather the faith of a few individuals in the proposition that many testing problems could be solved if a multifaceted industry could agree on a standard for all to follow. Four of these individuals stand out; they are Harry Bleeker, Colin Maunder, Rodham Tulloss, and Lee Whetsel. In that I am convinced that the 1149.1 standard is the most significant testing development in the last 20 years, I personally feel a debt of gratitude to them and all the people who labored on the various Working Groups in its creation.
Why Read This Book
You should read this book if you need a practical, standards-centered explanation of boundary-scan (JTAG) and how to use it for in-system programming, board interconnect test and debug. It walks you from the basics of IEEE 1149.1 architecture through BSDL and real-world test strategies, giving the concrete knowledge you can apply to FPGA bring-up and manufacturing test.
Who Will Benefit
Hardware and FPGA engineers, test/validation engineers, and board bring-up technicians who need to program, debug, and test FPGA-based boards and PCBs using JTAG/boundary-scan.
Level: Intermediate — Prerequisites: Basic digital logic and PCB familiarity, and a working knowledge of FPGAs or CPLDs; no deep prior boundary-scan expertise required.
Key Takeaways
- Explain the IEEE 1149.1 (JTAG) TAP architecture and how boundary-scan registers operate
- Create and interpret BSDL device descriptions and use them to derive test vectors
- Design and execute board-level interconnect tests and diagnose stuck-at/open faults using boundary-scan
- Use JTAG for in-system programming/configuration of FPGAs and CPLDs and integrate it into manufacturing flows
- Apply practical strategies for test access, chain topology, and mixed-device boards to improve test coverage
Topics Covered
- Introduction and history of boundary-scan and IEEE 1149.1
- Overview of JTAG: TAP controller, states and operations
- Boundary-scan register architecture and test data/instruction registers
- Device description language (BSDL): format, parsing, and use
- Board-level test strategies and interconnect testing techniques
- Creating and applying test vectors; fault models and diagnosis
- In-system programming and FPGA/CPLD configuration via JTAG
- Chain architectures, multi-device considerations, and TAP topology
- Practical tool workflows and vendor application notes
- Advanced topics: IEEE 1149.x extensions and mixed-signal considerations
- Case studies and worked examples
- Appendices: standards references, test scripts, and troubleshooting tips
Languages, Platforms & Tools
How It Compares
Compared with vendor application notes (e.g., Xilinx/Intel JTAG guides), this book provides a broader, standards-focused and vendor-neutral treatment of IEEE 1149.1 and board-level test strategies rather than just tool usage.
