Design Recipes for FPGAs, Second Edition: Using Verilog and VHDL
This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement.
- Examples are rewritten and tested in Verilog and VHDL
- Describes high-level applications as examples and provides the building blocks to implement them, enabling the student to start practical work straight away
- Singles out the most important parts of the language that are needed for design, giving the student the information needed to get up and running quickly
Why Read This Book
You will get a concise, practical toolbox of reusable Verilog and VHDL templates and proven design patterns that speed up real FPGA projects. The book focuses on how to synthesize, simulate and fit working HDL designs to devices, so you'll pick up immediately usable techniques rather than only theory.
Who Will Benefit
Engineers and advanced students who already know basic digital logic and want a compact set of practical HDL recipes to implement real-world FPGA functions quickly and robustly.
Level: Intermediate — Prerequisites: Basic digital logic (combinational and sequential circuits) and familiarity with at least one HDL (Verilog or VHDL) and basic FPGA toolflow concepts.
Key Takeaways
- Apply proven Verilog and VHDL templates for common functions (register files, FIFOs, arbiters, buses).
- Design and implement reliable finite-state machines and synchronous datapaths that synthesize well.
- Manage clock domains and implement safe clock-domain crossing techniques.
- Optimize HDL for synthesis, area, and timing on Xilinx and Intel/Altera FPGAs.
- Create effective testbenches and simulation flows to validate designs before downloading to hardware.
Topics Covered
- 1. Introduction to FPGA Design Recipes
- 2. Getting Started: Synthesis, Simulation and Toolflows
- 3. Combinational Building Blocks and Templates
- 4. Sequential Logic and Finite-State Machines
- 5. Registers, Pipelines and Datapath Design
- 6. Memory, FIFOs and RAM/ROM Templates
- 7. Interfaces and Peripheral Blocks (UART, SPI, I2C, etc.)
- 8. Clocking, Reset Strategies and Clock-Domain Crossing
- 9. Arithmetic and DSP-oriented Structures
- 10. Optimization for Synthesis: Area, Speed, and Resources
- 11. Testbenches, Verification and Simulation Techniques
- 12. Fitting Designs to Devices: Constraints and Implementation
- 13. Case Studies and Example Projects
- Appendices: Coding Guidelines and HDL Reference
Languages, Platforms & Tools
How It Compares
Similar in practical intent to Pong P. Chu's "FPGA Prototyping" books, but Wilson's book is more of a compact recipe book with reusable templates and design patterns rather than step-by-step lab exercises.
