Verilog Digital Computer Design: Algorithms into Hardware
Understand the fundamental goals, structure, and behavior of Verilog; Discover how to use ASMs as the "master plan" for digital design; Walk through the three stages of Verilog design: behavioral, mixed, and structural; Learn Verilog simulation techniques for Mealy machines and bottom-testing loops; Use Verilog simulation techniques to model propagation delay; Leverage special-purpose design techniques to build general-purpose processors; Build a CPU from a ready-to-synthesize programmable logic example. Verilog Digital Computer Design: Algorithms to Hardware is more than a great guide to Verilog: it's a primer on the enduring concepts of computer design that will apply no matter which tools you choose.
Why Read This Book
You should read this book if you want a hands-on, methodical path from algorithm and ASM charts to a synthesizable Verilog CPU. It teaches pragmatic design stages (behavioral, mixed, structural), useful simulation techniques, and concrete strategies for converting control and datapath ideas into working hardware.
Who Will Benefit
Engineers or advanced students who know basic digital logic and Verilog and want to design processors, controllers, or custom datapath logic and see a complete algorithm-to-hardware workflow.
Level: Intermediate — Prerequisites: Familiarity with basic digital logic (combinational/sequential circuits), finite-state machines, and basic Verilog syntax and simulation concepts.
Key Takeaways
- Use ASM charts to structure control and map algorithms into hardware-friendly state machines.
- Translate behavioral specifications into mixed- and structural-level Verilog suitable for synthesis.
- Design and simulate Mealy/Moore state machines and bottom-testing loops with Verilog testbenches.
- Model propagation delay and understand timing effects in simulation for more realistic designs.
- Apply special-purpose design techniques to construct general-purpose processors from building blocks.
- Assemble and prepare a complete CPU design for synthesis on programmable logic devices.
Topics Covered
- Introduction: Goals and Overview of Verilog-Based Design
- Verilog Fundamentals and Modeling Styles
- Algorithmic State Machines (ASMs) as a Design Framework
- Behavioral Design Stage: Specification and Simulation
- Mixed-Level Design: Bridging Algorithm and Structure
- Structural Design and Component Interconnection
- Finite-State Machines: Mealy and Moore Techniques
- Simulation Techniques: Timing, Delays, and Bottom-Testing
- Special-Purpose Techniques for Processor Building
- From Datapath and Control to a Synthesizable CPU
- Case Study: Building a General-Purpose Processor
- Synthesis Considerations and Programmable-Logic Implementation
- Appendices: Verilog Reference and Example Listings
Languages, Platforms & Tools
How It Compares
More focused on algorithm-to-hardware and CPU construction than Palnitkar's Verilog HDL (language reference) and more CPU-centered than Pong Chu's FPGA project books, which emphasize hands-on vendor-specific FPGA prototyping.
