Digital System Test and Testable Design: Using HDL Models and Architectures
This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.
Why Read This Book
You will get a hands-on, HDL-centered treatment of digital test: learn how to model fault simulation, ATPG, scan-based DFT and BIST in Verilog and evaluate hardware trade-offs. The book emphasizes practical Verilog implementations (including PLI) so you can prototype and measure test architectures before committing silicon or FPGA resources.
Who Will Benefit
FPGA/ASIC engineers and advanced students who design RTL in Verilog and need to add or evaluate design-for-test (DFT), built-in self-test (BIST), and testbench-based fault analysis.
Level: Advanced — Prerequisites: Solid understanding of digital logic and sequential design, familiarity with Verilog RTL and simulation; basic knowledge of scan concepts and timing is helpful.
Key Takeaways
- Implement scan-based DFT and common BIST architectures in Verilog
- Model and run fault-simulation algorithms and basic ATPG concepts using HDL testbenches
- Use Verilog PLI to extend simulation for test applications and fault injection
- Analyze on-chip compression/decompression schemes and quantify hardware/timing overheads
- Design test sessions and infrastructure (scan chains, test access) for complex digital systems
- Evaluate test coverage and apply practical trade-offs between test hardware and test time
Topics Covered
- Introduction to Testing and Testability
- Fault Models and Fault Equivalence
- Fault Simulation Techniques
- Automatic Test Pattern Generation (ATPG)
- Design-for-Testability: Scan Design and Scan Architectures
- Built-In Self-Test (BIST) Architectures
- On-Chip Test Data Compression and Decompression
- Boundary-Scan and Test Access Mechanisms (JTAG)
- Verilog Modeling for Test and Testbenches
- Using Verilog PLI for Test Applications and Fault Injection
- Test Session Design, Scheduling, and Test Control
- Case Studies and HDL Examples
- Practical Considerations: Area, Timing and Testability Trade-offs
Languages, Platforms & Tools
How It Compares
More hands-on and Verilog-centric than Abramovici/Breuer/Friedman's classic 'Digital Systems Testing', and more practical/HDL-focused than Bushnell & Agrawal's broad 'Essentials of Electronic Testing'.
