Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
- Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
- Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
- Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
- Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
Why Read This Book
You should read this book if you need a single, comprehensive reference that takes you through the entire EDA flow from ESL modeling to test. You will learn the core concepts, data structures, algorithms, and architectures that power synthesis, verification, and test tools — practical knowledge that helps you evaluate tools, design better RTL, or start building EDA components of your own.
Who Will Benefit
EDA engineers, VLSI designers, verification engineers, and graduate students who need practical fluency across synthesis, verification, and test to design, validate, or build tools for complex digital systems.
Level: Intermediate — Prerequisites: Basic digital logic and computer architecture, familiarity with RTL (Verilog/VHDL), undergraduate-level algorithms and data structures, and some exposure to ASIC/FPGA design flows.
Key Takeaways
- Understand the end-to-end EDA flow and how ESL, RTL synthesis, logic optimization, physical design, verification, and test fit together
- Apply core algorithms and data structures used in synthesis and verification, such as BDDs, SAT-based techniques, and graph algorithms
- Design and evaluate RTL-friendly coding and synthesis strategies to achieve timing, area, and power goals
- Implement and reason about formal and simulation-based verification methods, including equivalence checking and coverage-driven verification
- Evaluate DFT and scan strategies and incorporate testability considerations into logic and physical design
- Integrate high-level synthesis (HLS) and system-level modeling into the design flow for faster exploration and FPGA/ASIC mapping
Topics Covered
- 1. Overview of the EDA Flow and Design Methodologies
- 2. ESL and System-Level Modeling (SystemC, C/C++)
- 3. RTL Synthesis: Representations and Algorithms
- 4. Logic Optimization and Technology Mapping
- 5. Timing Analysis and Clocking Strategies (STA)
- 6. Formal Verification and Equivalence Checking
- 7. Simulation, Assertion-Based Verification, and Coverage
- 8. Physical Design: Floorplanning, Placement, and Routing
- 9. Design for Testability (DFT) and Fault Models
- 10. Test Generation, ATPG, and Built-In Self-Test (BIST)
- 11. High-Level Synthesis and Hardware/Software Co-Design
- 12. Reconfigurable Computing and FPGA-Specific Considerations
- 13. Tool Architectures, Data Structures, and Scalability
- 14. Case Studies, Benchmarks, and Emerging Directions
Languages, Platforms & Tools
How It Compares
Covers similar ground to Lavagno, Martin, and Scheffer's "Electronic Design Automation for Integrated Circuits Handbook" but places more emphasis on the underlying algorithms, data structures, and architectures that enable synthesis, verification, and test.
