SuperSpeed Device Design By Example
This is a "How-To" book which explains, with hands-on examples, how to design and implement a SuperSpeed USB peripheral that can interface to your hardware using a 32-bit 100MHz bus with standard or custom protocols. The book is based on the Cypress FX3 SuperSpeed Device and the firmware examples are written around a low-cost SuperSpeed Explorer board and a companion CPLD board which are available from www.cypress.com/fx3book. The software examples are written for the Windows operating system and the CPLD examples are written in Verilog. The source code for all of the examples is downloadable from the book web site. If you currently think that SuperSpeed USB design is only for the elite then look inside this book and discover that SuperSpeed technology has now been made accessible to the rest of us!
Why Read This Book
You will learn, by doing, how to design a SuperSpeed (USB 3.0) peripheral that connects to your custom hardware using a 32-bit, 100 MHz bus and standard or custom protocols. The book’s step‑by‑step examples around the Cypress FX3 SuperSpeed Explorer board and companion CPLD show you working FX3 firmware, Verilog CPLD code, and Windows host software so you can move quickly from concept to a running prototype.
Who Will Benefit
Embedded hardware and FPGA engineers (intermediate level) who need to add high‑speed USB 3.0 peripheral capability to their designs and want concrete, board‑level examples tying FX3 firmware to Verilog CPLD/FPGA interfaces.
Level: Intermediate — Prerequisites: Basic digital logic and familiarity with Verilog, C programming experience (for firmware and Windows host code), and a working knowledge of USB concepts (endpoints, descriptors, transfers).
Key Takeaways
- Design a SuperSpeed USB peripheral around the Cypress FX3 and map it to a 32‑bit, 100 MHz parallel bus.
- Implement FX3 firmware to configure endpoints, handle transfers, and interface with custom hardware protocols.
- Write and integrate Verilog CPLD logic to bridge the FX3 and your FPGA/CPLD-based hardware.
- Develop Windows host software to enumerate, control, and perform high‑throughput data transfers with the device.
- Debug and optimize throughput and reliability using practical test setups and downloadable example code.
Topics Covered
- Introduction to SuperSpeed USB and the FX3 Platform
- Overview of the SuperSpeed Explorer and CPLD Companion Board
- Hardware Interfaces: The 32‑bit, 100 MHz Bus and Signal Timing
- FX3 Architecture and Firmware Model
- USB Endpoints, Descriptors, and Transfer Types
- Building the FX3 Firmware: Examples and Patterns
- Verilog CPLD Examples: Bus Bridges and Protocol Adapters
- Windows Host Software: Drivers, APIs, and Sample Code
- Integration: Connecting FX3, CPLD, and FPGA
- Performance Tuning and Throughput Measurement
- Debugging Techniques: Logic Analyzers, USB Analyzers, and Logs
- Advanced Topics: Custom Protocols and Multi‑buffering
- Appendices: Schematics, Bill of Materials, and Source Code Access
Languages, Platforms & Tools
How It Compares
Compared to Jan Axelson’s 'USB Complete' (which focuses broadly on USB fundamentals and many device classes), this book is tightly focused on hands‑on Cypress FX3 SuperSpeed peripheral implementation with Verilog CPLD examples and ready‑to‑run Windows host code.
