Starter's Guide to Verilog 2001
Introducing the Verilog HDL in a brief format, this book presents a selected set of the changes the popular hardware underwent in its first revision—emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis. Chapter topics cover an Introduction to Digital Design Methodology; Basic Concepts: Primitives, Data Types, and Operators in Verilog; Modeling Structure with Verilog; Modeling Behavior with Verilog; and Modeling Finite-State Mechanics and Datapath Controllers with Verilog. For designers with no backgrounds in HDLs, and designers familiar with Verilog 1995 and interested in the new features of Verilog 2001.
Why Read This Book
You will get a compact, synthesis-focused introduction to IEEE Std 1364-2001 (Verilog-2001) that gets you writing practical, synthesizable HDL for combinational and sequential logic quickly. The book emphasizes real-world coding styles for FSMs and datapaths and highlights the Verilog-2001 features that matter most for FPGA and ASIC implementation.
Who Will Benefit
Beginner FPGA/ASIC designers, students, or engineers familiar with digital logic who need a short, pragmatic guide to Verilog-2001 and synthesis-friendly coding.
Level: Beginner — Prerequisites: Basic digital logic knowledge (Boolean algebra, combinational and sequential circuits) and comfort reading schematic/block diagrams; no prior HDL experience required.
Key Takeaways
- Write synthesizable Verilog-2001 modules using the language's primitives, data types, and operators.
- Model and implement combinational and sequential logic in both structural and behavioral styles.
- Design and code finite-state machines and datapath controllers with synthesis-friendly patterns.
- Apply practical synthesis guidelines and avoid common coding pitfalls that prevent hardware realization.
- Translate or update Verilog-1995 code to the Verilog-2001 style and features where beneficial.
Topics Covered
- Preface and How to Use This Book
- 1. Introduction to Digital Design Methodology
- 2. Overview of Verilog-2001 and Language Changes
- 3. Basic Concepts: Primitives, Data Types, and Operators
- 4. Modeling Structure with Verilog (Modules, Instances, Nets)
- 5. Modeling Behavior with Verilog (Procedures, Always Blocks, Blocking vs Nonblocking)
- 6. Combinational Logic Design and Coding Styles
- 7. Sequential Logic and Register Transfer Modeling
- 8. Finite-State Machine Design and Implementation
- 9. Datapath Controllers and Combining FSMs with Datapaths
- 10. Synthesis Considerations and Coding Guidelines
- 11. Examples and Small Design Case Studies
- Appendices: Language Reference, Common System Tasks, and Directives
Languages, Platforms & Tools
How It Compares
Compared with Samir Palnitkar's Verilog HDL, Ciletti's book is much shorter and more narrowly focused on Verilog-2001 and synthesis-friendly practice, while Palnitkar provides a broader tutorial and more examples; compared to Brown & Vranesic's textbook, Ciletti is less comprehensive on digital design theory and more concise on practical Verilog usage.
