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RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Stuart Sutherland ● 2017

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”

Why Read This Book

You will learn how to write SystemVerilog RTL that both simulates correctly and synthesizes predictably for ASIC and FPGA flows, with practical coding styles and anti-patterns to avoid. The book blends concise language reference with hands-on guidance so you can produce robust, tool-portable designs and avoid common simulation vs. synthesis pitfalls.

Who Will Benefit

Digital design engineers or FPGA/ASIC implementers with some HDL experience who want to produce clean, synthesizable SystemVerilog RTL and integrate it into real tool flows.

Level: Intermediate — Prerequisites: Basic digital logic and RTL design concepts (combinational/sequential logic, FSMs, registers, clocks and resets) and familiarity with an HDL (Verilog or VHDL recommended).

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Key Takeaways

  • Write synthesizable SystemVerilog RTL using modern, tool-portable coding styles
  • Distinguish simulation-only constructs from synthesizable constructs and avoid mismatches
  • Model common hardware structures (FSMs, pipelines, memories, FIFOs, buses) in a synthesis-friendly way
  • Apply interfaces, packages, and clocking blocks to organize code and improve reuse and verification
  • Map RTL intent to FPGA/ASIC resources and anticipate synthesis/implementation tool behavior
  • Use assertions, coverage, and disciplined testbench practices to improve functional correctness

Topics Covered

  1. 1. Introduction: SystemVerilog for Design and Synthesis
  2. 2. SystemVerilog Data Types and Expressions: What Synthesizes
  3. 3. Modules, Interfaces, and Packages: Code Organization
  4. 4. Combinational and Sequential RTL Coding Styles
  5. 5. Finite State Machines and Control Structures
  6. 6. Memories, Arrays, and RAM/ROM Inference
  7. 7. Clocking, Reset Strategies, and Clock Domain Crossing
  8. 8. Concurrency, Nonblocking vs Blocking Assignments, and Race Conditions
  9. 9. RTL for FIFOs, Pipelines, and Streaming Interfaces
  10. 10. Simulation vs Synthesis Semantics and Common Pitfalls
  11. 11. Assertions, Formal-friendly Coding, and Coverage
  12. 12. Integration with FPGA/ASIC Tool Flows and Constraints
  13. 13. Synthesis Case Studies and Coding Anti-patterns
  14. 14. Testbench Patterns and Verification Guidance
  15. Appendices: SystemVerilog Reference and Synthesis Guidelines

Languages, Platforms & Tools

SystemVerilogVerilogVHDL (comparative mentions)Xilinx FPGAs (Vivado/7-series/Zynq families)Intel/Altera FPGAs (Quartus)ASIC synthesis flowsXilinx Vivado (synthesis/implementation)Intel Quartus PrimeSynopsys Design CompilerCadence/Siemens EDA tools (synthesis and simulation)Mentor/Siemens ModelSim/Questa for simulationVivado HLS / Intel HLS (contextual discussion)

How It Compares

More focused on synthesis-friendly SystemVerilog RTL than Palnitkar's Verilog HDL (which is introductory Verilog), and more implementation-oriented than verification books like 'SystemVerilog for Verification' — it bridges language reference and practical synthesis guidance.

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