Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Behavioral Synthesis: A Practical Guide to High-Level Design includes details on new material and new interpretations of old material with an emphasis on practical information. The intended audience is the ASIC (or high-end FPGA) designer who will be using behavioral synthesis, the manager who will be working with those designers, or the engineering student who is studying leading-edge design techniques.
Today's designs are creating tremendous pressures for digital designers. Not only must they compress more functionality onto a single IC, but this has to be done on shorter schedules to stay ahead in extremely competitive markets. To meet these opposing demands, designers must work at a new, higher level of abstraction to efficiently make the kind of architectural decisions that are critical to the success of today's complex designs. In other words, they must include behavioral design in their flow.
The biggest challenge to adopting behavioral design is changing the mindset of the designer. Instead of describing system functionality in great detail, the designer outlines the design in broader, more abstract terms. The ability to easily and efficiently consider multiple design alternatives over a wide range of cost and performance is an extremely persuasive reason to make this leap to a high level of abstraction. Designers that learn to think and work at the behavioral level will reap major benefits in the resultant quality of the final design.
But such changes in methodology are difficult to achieve rapidly. Education is essential to making this transition. Many designers will recall the difficulty transitioning from schematic-based design to RTL design. Designers that were new to the technology often felt that they had not been told enough about how synthesis worked and that they were not taught how to effectively write HDL code that would synthesize efficiently.
Using this unique book, a designer will understand what behavioral synthesis tools are doing (and why) and how to effectively describe their designs that they are appropriately synthesized.
CD ROM INCLUDED!
The accompanying CD-ROM contains the source code and test benches for the three case studies discussed in Chapters 14, 15 and 16.
Why Read This Book
You should read this book if you need a pragmatic, hands-on road map for applying behavioral (high-level) synthesis to real ASIC and high-end FPGA designs — it shows how to move up the abstraction ladder so you can make better architectural tradeoffs under tight schedules. You will learn practical coding styles, transformation techniques, and how to translate algorithmic descriptions into efficient RTL while managing area, performance, and verification concerns.
Who Will Benefit
Ideal for intermediate ASIC or high-end FPGA designers, engineering managers coordinating synthesis-driven projects, and graduate/advanced undergraduate students studying high-level design techniques.
Level: Intermediate — Prerequisites: Solid understanding of digital logic and RTL design fundamentals and familiarity with a hardware description language such as Verilog or VHDL; basic knowledge of synthesis and timing concepts.
Key Takeaways
- Apply behavioral synthesis techniques to convert algorithmic descriptions into optimized RTL suitable for ASICs and high-end FPGAs
- Evaluate and make architectural trade-offs between area, latency, throughput, and power at a high level
- Optimize high-level code and coding styles to guide synthesis tools toward better schedules, resource sharing, and pipelining
- Integrate HLS-generated RTL into conventional ASIC and FPGA design flows and manage downstream synthesis/place-and-route issues
- Design and implement verification strategies for synthesized blocks, including testbench generation and cycle-accurate checking
Topics Covered
- 1. Introduction to Behavioral Synthesis and Motivation
- 2. High-Level Descriptions: Algorithms, Datapaths, and Control
- 3. Languages and Coding Styles for Synthesis (C-like, VHDL, Verilog Considerations)
- 4. Scheduling: Time Partitioning and Latency Management
- 5. Allocation and Binding: Mapping Operations to Resources
- 6. Resource Sharing, Functional Units, and Memory Architectures
- 7. Pipelining and Retiming for Throughput
- 8. Timing, Area, and Power Trade-offs in High-Level Design
- 9. Verification, Testbenches, and Validation of Synthesized RTL
- 10. Integrating HLS into ASIC and High-End FPGA Flows
- 11. Case Studies and Real-World Examples
- 12. Practical Tool Use, Workflow, and Project Management
- 13. Future Directions in Behavioral Synthesis and Reconfigurable Computing
Languages, Platforms & Tools
How It Compares
More practically focused than academic treatments such as Philippe Coussy's High-Level Synthesis texts, Elliott's book emphasizes hands-on design patterns and flow integration rather than formal theory; compared to Wayne Wolf's C-based design works, it is more narrowly focused on behavioral synthesis and RTL mapping.
