StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Victor Yurkovsky

Summary: Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes. Part 2:...


StrangeCPU #2. Sliding Window Token Machines

Victor Yurkovsky

Summary: An in-depth exploration of Sliding Window Token Machines; ARM notes. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token...


StrangeCPU #1. A new CPU

Victor Yurkovsky

Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton

Introduction This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an...


MyHDL FPGA Tutorial I (LED Strobe)

Christopher Felton
2 comments

Last updated 05-Nov-2015Introduction From many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources.  Even the devices that one can get for sub \$10 are relatively large. ...


Using GHDL for interactive simulation under Linux

Martin Strubel
2 comments

The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I...


VHDL tutorial - A practical example - part 3 - VHDL testbench

Gene Breniman

In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part.  In part 2, we described the VHDL logic of the CPLD for this design.  In part...


Verilog vs VHDL

Muhammad Yasir

Introduction   Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL...


Developing FPGA-DSP IP with Python

Christopher Felton
2 comments

This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has...


New Design - Finally!

Stephane Boucher

For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for...