Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Introduction This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product....
I don’t often convert VHDL to Verilog but when I do ...
VHDL to Verilog I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL. The...
BGA and QFP at Home 1 - A Practical Guide.
It is almost universally accepted by the hobbyists that you can't work with high-density packages at home. That is entirely incorrect. I've been assembling and reflowing BGA circuit boards at home for a few years now. BGAs and...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did. Will everyone, at some future point, also buy an FPGA? The market size...
StrangeCPU #4. Microcode
Summary: Sliding windows containing runs of microcode. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token Machines, an...
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Summary: Decoding instructions with a Sliding Window system. 0-Bit Sliding Register Windows. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2:...
StrangeCPU #2. Sliding Window Token Machines
Summary: An in-depth exploration of Sliding Window Token Machines; ARM notes. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token...
StrangeCPU #1. A new CPU
Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even...
MyHDL FPGA Tutorial II (Audio Echo)
Introduction This tutorial will walk through an audio echo that can be implemented on an FPGA development board. This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial. This project will require an...
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
IntroductionA well known algorithm for computing square roots by iteration is provided by the Newton-Raphson Algorithm. The algorithm determines the square root using iteration until the root has been determined to some user-defined level of...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to Verilog I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am...
StrangeCPU #4. Microcode
Summary: Sliding windows containing runs of microcode. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token Machines, an...
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Summary: Decoding instructions with a Sliding Window system. 0-Bit Sliding Register Windows. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2:...
StrangeCPU #1. A new CPU
Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even...
StrangeCPU #2. Sliding Window Token Machines
Summary: An in-depth exploration of Sliding Window Token Machines; ARM notes. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token...
New Design - Finally!
For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL. The...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
