transfert data from host pc to target fpga using DMA

Started by assaad 3 years ago6 replieslatest reply 3 years ago169 views
I have 2 image files imported by ENVI tool (png or raster file), and they are stored in my hard disk, I want to transfer this data from host PC to target FPGA using...

Currently at Embedded World

Started by stephaneb 3 years ago5 replieslatest reply 3 years ago274 views
I am currently at Embedded World in Germany (tomorrow is the last day) and with more than 1000 vendors, most relevant players in the industry are here this week.I...

Is this an FPGA job spec or a lecture on FPGA?

Started by kaz 3 years ago101 views
A current active contract role for an FPGA engineer  is around but sounds very strange in that it tries to explain the FPGA more than the required skills for the...

FPGA perspective of pins versus PCB perspective

Started by kaz 3 years ago2 replieslatest reply 3 years ago58 views
Hi All,I am looking for any hints on  FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...

Ideas for simple bitrate regulation

Started by Kamilpl 3 years ago5 replieslatest reply 3 years ago152 views
Hello everyone,I would like to implement a bitrate regulation on an fpga board.Clock + data are incoming at bitrate with a +/- percentage. Then after a channel coder...

If FPGAs didn't work we won't be here?

Started by kaz 3 years ago2 replieslatest reply 3 years ago99 views
Being over-careful  is good practice especially for presentation to the management but factual issues should not be distorted for that sake.What I mean if an FPGA...

Greatest Conferences?

Started by stephaneb 3 years ago5 replieslatest reply 3 years ago374 views
I have been juggling with the idea to organize a DSP+Embedded+FPGA conference for a while now.  But I won't do it until I feel I can organize an event where everyone...

When (and why) is it a good idea to use an FPGA in your embedded system design?

Started by stephaneb 3 years ago11 replieslatest reply 3 years ago6300 views
Once we are done with this thread, the vision is for readers to get a basic understanding of when should an FPGA be considered in the design of an Embedded System...


Started by DK999 3 years ago11 replieslatest reply 3 years ago1449 views
Hi guys!So far I've made two versions of the IIR, one is more async (IIR_Biquad_II.vhd) and one uses a state machine (IIR State). The more async one was derived...

Timing constraints priority

Started by kaz 3 years ago1 replylatest reply 3 years ago733 views
Hi All,I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). Suppose I set clock group command to say clk1 is unrelated...

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