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Hi guys!So far I've made two versions of the IIR, one is more async (IIR_Biquad_II.vhd) and one uses a state machine (IIR State). The more async one was derived...
Started by Hi All,I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). Suppose I set clock group command to say clk1 is unrelated...
Got syntax errors in both mainboard and uart-receiver files
Started by 6 years ago●2 replies●latest reply 6 years ago●102 viewsI want to design a UART receiver/transmitter and by now I already developed the receiver vhdl file but when declare and instantiate the the receiver component on...
I have downloaded Xilinx 14.7 recently to implement partial reconfiguration on spartan 3E fpga. we need to indicate the project as partially reconfigurable at the...
Hi All,I need to create an AGC algorithm on FPGA. I am using some basic algorithm, but I receive input signal in every clock cycle.In AGC algorithm, in case I have...
I am currently working on an old board which have old FPGA SPRTAN which its not available on market on board and i dont have a source code for those FPGA's except...
1st project having issues with latches?
Started by 7 years ago●11 replies●latest reply 7 years ago●103 viewsHello,
So I am new to FPGA's and thought I would start an easy project which tries to recreate the Motorola MC14514 or 4 bit transparent latch/ 4 to 16 line decoder....
hey, I'll give a little background before I start, I've recently started with FPGA (I'm more used to PIC MCUs), which I'm planning to use with a high speed analog...
Reduce Phase of a filtered data set
Started by 7 years ago●3 replies●latest reply 7 years ago●68 viewsHi :)So when you filter data sets using moving average, median or any other filter, they produce some kind of shift and they cant properly follow the original...
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