Flip-Flops & Latches
Giving circuits memory
Everything we've built so far (gates, MUXes, adders) is combinational: the output depends only on the current inputs. But real circuits need memory. They need to remember a value and hold it, even when the input changes.
That's what flip-flops do. They're the fundamental memory element in every synchronous digital circuit, and there are dozens of them in every FPGA logic block.
Timing Diagram: Latch vs Flip-Flop
Click the D input row to set data values, then watch how Q responds differently in latch vs flip-flop mode:
From Latches to Flip-Flops
A latch is the simplest memory element. When its enable signal is high, the output follows the input (it's "transparent"). When enable goes low, the output holds its last value. The problem: while the latch is transparent, any input glitch passes straight through to the output.
A flip-flop solves this by only looking at the input at one precise moment: the clock edge. A positive-edge-triggered D flip-flop captures whatever value is on its D input at the instant the clock transitions from 0 to 1. Between clock edges, the output Q is locked. No matter what D does, Q doesn't change.
This is enormously important for reliable design. If all flip-flops in a circuit use the same clock, they all update at the same instant. Outputs from one stage become stable inputs for the next stage. This is the foundation of synchronous design, the methodology used in virtually all FPGAs.
The D flip-flop is by far the most common type. In FPGA designs, you'll use it constantly: every register, every pipeline stage, every state machine uses D flip-flops. Each CLB in an FPGA contains several of them, ready to use.
Why This Matters for FPGA Design
- Every CLB has flip-flops - they're free to use and the synthesis tool will infer them from your HDL
- Pipelining - adding flip-flop stages between combinational logic allows higher clock speeds
- State machines - FSM state registers are flip-flops
- Timing closure - understanding how data moves between flip-flops is essential for meeting timing
Frequently Asked Questions
What is a flip-flop?
A flip-flop is a circuit that stores one bit of data. It captures its input value at a specific moment (the rising or falling edge of a clock signal) and holds that value until the next clock edge. The D flip-flop is the most common type: on each clock edge, the output Q takes the value of input D and holds it. Flip-flops are the fundamental memory element in all synchronous digital circuits.
What is the difference between a latch and a flip-flop?
A latch is level-sensitive: it passes input to output whenever the enable signal is high (transparent). A flip-flop is edge-sensitive: it only captures the input at the precise moment of a clock edge, then holds it. In FPGA design, flip-flops are strongly preferred because edge-triggered behavior makes timing predictable and avoids glitches that can occur with level-sensitive latches.
What is edge triggering?
Edge triggering means the flip-flop responds only to the transition of the clock signal, not its level. A positive-edge-triggered flip-flop captures data at the instant the clock goes from 0 to 1. Between edges, the output is locked regardless of input changes. This creates clean, synchronized behavior where all flip-flops in a circuit update at the same moment.
Quick Check
Test your understanding of the key concepts from this lesson.
