FPGA Architecture

In the last lesson, you saw how look-up tables can implement any logic function. But a single LUT sitting alone isn't very useful. You need thousands of them, connected together, with access to the outside world.

Let's open up an FPGA chip and look inside. What you'll find is a carefully organized city of logic blocks, memory towers, math units, and a vast network of programmable wires connecting them all. Understanding this architecture is the key to writing efficient hardware, because in FPGA design, where your logic lives matters just as much as what it does.

Inside the Chip

This is a simplified floorplan of an FPGA. Click on any block to zoom in and see its internal structure:

The Five Building Blocks

Configurable Logic Blocks (CLBs) are the workhorses of the FPGA. Each CLB contains a small number of LUTs (typically two to eight, depending on the FPGA family), flip-flops for storing state, multiplexers for routing signals within the block, and carry-chain logic that makes arithmetic fast. CLBs are arranged in a regular grid across the chip, and a modern mid-range FPGA might have tens of thousands of them.

The Routing Fabric is the network of programmable wires and switches that connects everything together. Between every row and column of CLBs run channels of wires, including short wires for nearby connections and long wires that span the chip. Programmable switches at each intersection determine which wires connect to which. The routing fabric consumes the majority of the FPGA's silicon area and is often the factor that limits how fast your design can run.

I/O Blocks (IOBs) sit around the perimeter of the chip and connect the internal logic to the outside world. Each IOB can be configured as an input, output, or bidirectional pin, and supports various voltage standards and signaling protocols. Some IOBs support high-speed differential signaling for interfaces like DDR memory, PCIe, or high-speed serial links.

Block RAM (BRAM) provides fast, dedicated on-chip memory. BRAM columns are distributed across the chip, each block typically holding 18 or 36 kilobits. They support dual-port access (two independent reads or writes per clock cycle), making them ideal for FIFOs, buffers, and lookup tables that need to be accessed by different parts of your design simultaneously.

DSP Slices are hardwired multiply-accumulate units. Instead of building multipliers from LUTs (which would consume hundreds of them), DSP slices provide dedicated silicon that performs multiplication and addition in a single clock cycle. They are essential for signal processing, filtering, and any math-heavy computation. Like BRAM, DSP slices are arranged in columns across the chip.

Why This Matters

Understanding FPGA architecture helps you write better HDL. When you know that your design will be mapped onto CLBs connected by routing wires, you start thinking differently:

• You use BRAM instead of arrays of flip-flops when you need storage, because BRAM is there for exactly that purpose.
• You use DSP slices for multiplication instead of letting the tools build multipliers from LUTs.
• You keep related logic close together so routing delays don't kill your clock speed.
• You understand why the tools report resource utilization in terms of LUTs, flip-flops, BRAM, and DSP, because those are the physical resources on the chip.

The best FPGA designers have a mental model of the chip. This lesson gives you that model.